Stacked bit line dual word line nonvolatile memory
First Claim
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1. A method of forming a memory device, comprising:
- forming a first conductive line and a conductive pad coupled to the first conductive line;
forming a first conductive element coupled to the first conductive line, the first conductive element orthogonal to the first conductive line;
forming second and third conductive elements orthogonal to the first conductive element;
forming a first memory cell between the second and first conductive elements on a sidewall beside the first conductive element; and
forming a second memory cell between the third and first conductive elements on the sidewall beside the first conductive element, wherein the first memory cell is over the second memory cell, and the sidewall extends from the first memory cell to the second memory cell.
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Abstract
An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
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Citations
30 Claims
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1. A method of forming a memory device, comprising:
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forming a first conductive line and a conductive pad coupled to the first conductive line; forming a first conductive element coupled to the first conductive line, the first conductive element orthogonal to the first conductive line; forming second and third conductive elements orthogonal to the first conductive element; forming a first memory cell between the second and first conductive elements on a sidewall beside the first conductive element; and forming a second memory cell between the third and first conductive elements on the sidewall beside the first conductive element, wherein the first memory cell is over the second memory cell, and the sidewall extends from the first memory cell to the second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming a memory device, comprising:
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forming first and second conductive lines extending in a first direction; forming a first conductive element coupled to the first conductive line; forming a second conductive element coupled to the second conductive line, wherein the first and second conductive elements are disposed along a line extending in the first direction; forming a first memory cell on a first sidewall of the first conductive element; and forming a second memory cell on a second sidewall of the second conductive element. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method of forming a memory device, comprising:
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forming a first conductive element; forming second and third conductive elements extending in a first direction; forming a fourth conductive element, the first and fourth conductive elements arranged in a second direction, the second direction different than the first direction; forming a first memory cell between the second and first conductive elements; forming a second memory cell between the third and first conductive elements; and forming a third memory cell between the second and fourth conductive elements; forming a first conductive line coupled to the first conductive element, the first conductive line orthogonal to the first conductive element, wherein the second and third conductive elements are orthogonal to the first conductive element, the fourth conductive element is orthogonal to the second and third conductive elements, and the first memory cell is over the second memory cell, wherein the first memory cell is chosen by selecting the first and second conductive elements, the second memory cell is chosen by selecting the first and third conductive elements, and the third memory cell is chosen by selecting the second and fourth conductive elements. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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Specification