Stacked bit line dual word line nonvolatile memory

• US 9,799,663 B2
• Filed: 08/26/2016
• Issued: 10/24/2017
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US15/249,025
• Publication Number:
  US 20160365349A1
• Time in Patent Office: 424 Days
• Field of Search: 438131, 257209, 257E23147, 257E29166
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. A method of forming a memory device, comprising:

forming a first conductive line and a conductive pad coupled to the first conductive line;

forming a first conductive element coupled to the first conductive line, the first conductive element orthogonal to the first conductive line;

forming second and third conductive elements orthogonal to the first conductive element;

forming a first memory cell between the second and first conductive elements on a sidewall beside the first conductive element; and

forming a second memory cell between the third and first conductive elements on the sidewall beside the first conductive element, wherein the first memory cell is over the second memory cell, and the sidewall extends from the first memory cell to the second memory cell.

2. The method of claim 1, further comprising:

forming a second conductive line parallel to the first conductive line; and

forming a fourth conductive element orthogonal to and coupled to the second conductive line.

3. The method of claim 2, further comprising:

forming a fifth conductive element orthogonal to and coupled to the second conductive line.

4. The method of claim 3, further comprising:

forming sixth and seventh conductive elements orthogonal to the fifth conductive element.

5. The method of claim 4, further comprising:

forming a third memory cell between the sixth and fifth conductive elements; and

forming a fourth memory cell between the seventh and fifth conductive elements, wherein the third memory cell is over the fourth memory cell.

6. The method of claim 2, further comprising:

forming eighth and ninth conductive elements orthogonal to the fourth conductive element.

7. The method of claim 6, further comprising:

forming a fifth memory cell between the eighth and fourth conductive elements; and

forming a sixth memory cell between the ninth and fourth conductive elements, wherein the fifth memory cell is over the sixth memory cell.

8. The method of claim 6, further comprising:

forming a seventh memory cell between the eighth conductive element and a tenth conductive element on a sidewall beside the tenth conductive element; and

forming an eighth memory cell between the ninth and tenth conductive elements on the sidewall beside the tenth conductive element, wherein the seventh memory cell is over the eighth memory cell.

9. The method of claim 2, wherein the first conductive line is disposed on a first horizontal plane and the second conductive line is disposed on a second horizontal plane different than the first horizontal plane.

10. The method of claim 2, wherein the conductive pad is disposed over the second conductive line.

11. A method of forming a memory device, comprising:

forming first and second conductive lines extending in a first direction;

forming a first conductive element coupled to the first conductive line;

forming a second conductive element coupled to the second conductive line, wherein the first and second conductive elements are disposed along a line extending in the first direction;

forming a first memory cell on a first sidewall of the first conductive element; and

forming a second memory cell on a second sidewall of the second conductive element.

12. The method of claim 11, further comprising:

forming a third conductive element orthogonal to the first conductive element; and

forming a fourth conductive element orthogonal to the second conductive element,

wherein the third conductive element is over the fourth conductive element, the first conductive element is orthogonal to the first conductive line, and the second conductive element is orthogonal to the second conductive line.

13. The method of claim 12, wherein the first memory cell is between the first conductive element and the third conductive element.

14. The method of claim 13, wherein the second memory cell is between the second conductive element and the fourth conductive element.

15. The method of claim 14, further comprising forming a fifth conductive element orthogonal to the first conductive element.

16. The method of claim 15, further comprising forming a sixth conductive element orthogonal to the second conductive element.

17. The method of claim 16, further comprising forming a third memory cell between the fifth conductive element and the first conductive element.

18. The method of claim 17, further comprising forming a fourth memory cell between the sixth conductive element and the second conductive element.

19. The method of claim 18, wherein the fourth memory cell is over the third memory cell.

20. The method of claim 11, wherein the second conductive element is coupled to the second conductive line through a conductive pad.

21. The method of claim 20, wherein the first conductive line is disposed on a first horizontal plane and the conductive pad is disposed on a second horizontal plane different than the first horizontal plane.

22. The method of claim 11, wherein the first conductive line is disposed on a first horizontal plane and the second conductive line is disposed on a second horizontal plane different than the first horizontal plane.

23. A method of forming a memory device, comprising:

forming a first conductive element;

forming second and third conductive elements extending in a first direction;

forming a fourth conductive element, the first and fourth conductive elements arranged in a second direction, the second direction different than the first direction;

forming a first memory cell between the second and first conductive elements;

forming a second memory cell between the third and first conductive elements; and

forming a third memory cell between the second and fourth conductive elements;

forming a first conductive line coupled to the first conductive element, the first conductive line orthogonal to the first conductive element, wherein the second and third conductive elements are orthogonal to the first conductive element, the fourth conductive element is orthogonal to the second and third conductive elements, and the first memory cell is over the second memory cell,

wherein the first memory cell is chosen by selecting the first and second conductive elements, the second memory cell is chosen by selecting the first and third conductive elements, and the third memory cell is chosen by selecting the second and fourth conductive elements.

24. The method of claim 23, further comprising:

forming a fifth conductive element orthogonal to and coupled to the first conductive line.

25. The method of claim 24, further comprising:

forming sixth and seventh conductive elements orthogonal to the fifth conductive element.

26. The method of claim 25, further comprising:

forming a fourth memory cell between the sixth and fifth conductive elements; and

a fifth memory cell between the seventh and fifth conductive elements, wherein the fourth memory cell is over the fifth memory cell.

27. The method of claim 23, further comprising:

forming a second conductive line coupled to the fourth conductive element through a conductive pad, the second conductive line orthogonal to the fourth conductive element.

28. The method of claim 27, wherein the first conductive line is disposed on a first horizontal plane and the second conductive line is disposed on a second horizontal plane different than the first horizontal plane.

29. The method of claim 27, wherein the first conductive line is disposed on a first horizontal plane and the conductive pad is disposed on a second horizontal plane different than the first horizontal plane.

30. The method of claim 23, wherein the first direction is orthogonal to the second direction.