Capacitor structures, decoupling structures and semiconductor devices including the same

• US 9,799,724 B2
• Filed: 06/05/2015
• Issued: 10/24/2017
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-Min, Jun, Jongryul, Kim, Eun A, Lim, Jung-Bum
• Primary Examiner(s): Tran, Minh-Loan
• Application Number:
  US14/732,278
• Publication Number:
  US 20160073502A1
• Time in Patent Office: 872 Days
• Field of Search: None
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 28/86 having horizontal extensions
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 28/92 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H10B 12/02 for one transistor one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments

Abstract

Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.

Claims

1. An integrated circuit device, comprising:

a decoupling structure having a first capacitor and a second capacitor that is different from the first capacitor, the decoupling structure comprising;

a first plurality of conductive patterns that each extend in a vertical direction;

a second plurality of conductive patterns that each extend in the vertical direction;

a horizontally disposed unitary supporting structure that structurally supports the first plurality of conductive patterns and the second plurality of conductive patterns; and

a common electrode disposed between ones of the first plurality of conductive patterns and between ones of the second plurality of conductive patterns,

wherein the first plurality of conductive patterns and the common electrode comprise electrodes of the first capacitor, and the second plurality of conductive patterns and the common electrode comprise electrodes of the second capacitor,

wherein the first plurality of conductive patterns and the second plurality of conductive patterns are horizontally spaced apart from each other in a first direction with a separation region therebetween,

wherein the decoupling structure is mounted on an underlying lower structure so that the lower structure and the decoupling structure are stacked in the vertical direction, and the unitary supporting structure comprises a plurality of openings when viewed from above, and

wherein none of the plurality of openings extend into the separation region.

2. The integrated circuit device of claim 1, wherein a minimum width of each of the plurality of openings is less than two times a thickness in the vertical direction of a portion of the common electrode that is disposed on an upper surface of the unitary supporting structure.

3. The integrated circuit device of claim 1, wherein a width of the separation region in the first direction is less than two times a thickness in the vertical direction of a portion of the common electrode that is disposed on an upper surface of the unitary supporting structure.

4. The integrated circuit device of claim 1, wherein:

a first portion of the common electrode overlies an upper surface of the unitary supporting structure; and

an upper surface of the first portion of the common electrode is disposed at a level higher than an upper surface of each of the first plurality of conductive patterns.

5. The integrated circuit device of claim 4, wherein the upper surface of the unitary supporting structure is disposed at a level higher than the upper surface of the each of the first plurality of conductive patterns.

6. The integrated circuit device of claim 1, further comprising:

a substrate underneath the decoupling structure; and

a pair of conductive plates disposed between the substrate and the common electrode, wherein;

the pair of conductive plates comprises a first conductive plate that is electrically connected to the first plurality of conductive patterns and a second conductive plate that is electrically connected to the second plurality of conductive patterns; and

the first conductive plate and the second conductive plate are horizontally spaced apart from each other with a gap therebetween, the gap being disposed between the first plurality of conductive patterns and the second plurality of conductive patterns.

7. The integrated circuit device of claim 6, further comprising an insulating pattern between the pair of conductive plates and the common electrode, wherein the insulating pattern comprises an upper portion and a lower portion that protrudes toward the substrate in the gap between the first conductive plate and the second conductive plate.

8. The integrated circuit device of claim 6, further comprising a third conductive plate between the pair of conductive plates and the substrate.

9. The integrated circuit device of claim 8, wherein the first conductive plate and the third conductive plate comprise electrodes of a third capacitor, and the second conductive plate and the third conductive plate comprise electrodes of a fourth capacitor that is different from the third capacitor.

10. The integrated circuit device of claim 9, wherein:

the first capacitor and the second capacitor are connected in series, and the third capacitor and the fourth capacitor are connected in series; and

the first capacitor and the second capacitor are connected in parallel to the third capacitor and the fourth capacitor.

11. The integrated circuit device of claim 6, wherein:

the gap between the first conductive plate and the second conductive plate comprises a first gap; and

the integrated circuit device further comprises a third conductive plate and a fourth conductive plate between the pair of conductive plates and the substrate, wherein;

the third conductive plate and the fourth conductive plate are horizontally spaced apart from each other with a second gap therebetween;

the second gap is disposed between the first plurality of conductive patterns and the second plurality of conductive patterns; and

the first conductive plate and the third conductive plate comprise electrodes of a third capacitor, and the second conductive plate and the fourth conductive plate comprise electrodes of a fourth capacitor that is different from the third capacitor.

12. The integrated circuit device of claim 1, wherein each of the first plurality of conductive patterns has a height at least 20 times greater than a width of the each of the first plurality of conductive patterns.

13. The integrated circuit device of claim 1, wherein an unfilled void is disposed underneath the unitary supporting structure.

14. The integrated circuit device of claim 1, wherein the first plurality of conductive patterns and the second plurality of conductive patterns are spaced apart from the separation region.

15. The integrated circuit device of claim 1, wherein the first plurality of conductive patterns and the second plurality of conductive patterns are not disposed in the separation region.

16. A decoupling structure, comprising:

a plurality of vertically disposed electrode patterns on a substrate, the plurality of electrode patterns comprising;

first electrode patterns disposed along a first horizontal direction at a first interval; and

second electrode patterns disposed along the first horizontal direction at a second interval, wherein the first electrode patterns and the second electrode patterns are spaced apart from each other in the first horizontal direction with a separation region therebetween, and the separation region has a width in the first horizontal direction greater than the first interval or the second interval;

a unitary supporting structure at least partially surrounding respective sidewalls of the first electrode patterns and respective sidewalls of the second electrode patterns, wherein the unitary supporting structure comprises a plurality of openings when viewed from a plan perspective, and none of the plurality of openings extend into the separation region; and

a common electrode disposed between ones of the first electrode patterns and between ones of the second electrode patterns.

17. The decoupling structure of claim 16, wherein the unitary supporting structure extends across the separation region.

18. The decoupling structure of claim 16, wherein the first interval and the second interval are substantially equal.

19. The decoupling structure of claim 16, wherein the decoupling structure further comprises a first capacitor and a second capacitor that is different from the first capacitor,

wherein the first electrode patterns collectively comprise a first electrode of the first capacitor, and the common electrode comprises a second electrode of the first capacitor, and

wherein the second electrode patterns collectively comprise a first electrode of the second capacitor, and the common electrode comprises a second electrode of the second capacitor.

20. The decoupling structure of claim 19, further comprising:

a pair of conductive plates underneath the plurality of electrode patterns, wherein the pair of conductive plates comprises a first conductive plate that is electrically connected to the first electrode patterns and a second conductive plate that is electrically connected to the second electrode patterns.