Method for forming group III/V conformal layers on silicon substrates

• US 9,799,737 B2
• Filed: 06/17/2016
• Issued: 10/24/2017
• Est. Priority Date: 03/30/2012
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Bao, Xinyu, Sanchez, Errol Antonio C., Carlson, David K., Ye, Zhiyuan
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Newton, Valerie N
• Application Number:
  US15/185,749
• Publication Number:
  US 20160343811A1
• Time in Patent Office: 494 Days
• Field of Search: 438681, 438906
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02455 Group 13/15 materials
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: Y10T 117/1008 with responsive control means

Abstract

A method for forming a conformal group III/V layer on a silicon substrate and the resulting substrate with the group III/V layers formed thereon. The method includes removing the native oxide from the substrate, positioning a substrate within a processing chamber, heating the substrate to a first temperature, cooling the substrate to a second temperature, flowing a group III precursor into the processing chamber, maintaining the second temperature while flowing a group III precursor and a group V precursor into the processing chamber until a conformal layer is formed, heating the processing chamber to an annealing temperature, while stopping the flow of the group III precursor, and cooling the processing chamber to the second temperature. Deposition of the III/V layer may be made selective through the use of halide gas etching which preferentially etches dielectric regions.

Claims

1. A method of forming a layer, comprising:

positioning a substrate in a processing chamber, the substrate comprising an exposed surface;

delivering a nucleation gas comprising a first group III precursor to the exposed surface of the substrate while depositing a nucleation layer on the exposed surface, the nucleation gas being free of a group V precursor;

delivering a second group III precursor and a group V precursor to the nucleation layer while depositing a group III/V layer on the nucleation layer; and

continuing to flow the group V precursor while stopping the flow of the second group III precursor.

2. The method of claim 1, wherein the processing chamber is heated to from about 550°

C. to about 650°

C. prior to delivering the nucleation gas comprising the first group III precursor.

3. The method of claim 2, wherein the processing chamber is cooled to about 250°

C. to about 400°

C. after the processing chamber is heated and prior to delivering the nucleation gas comprising the first group III precursor.

4. The method of claim 3, wherein the processing chamber is heated to about 450°

C. to about 550°

C. while stopping the flow of the second group III precursor.

5. The method of claim 1, wherein the first group III precursor and the second group III precursor are aluminum, gallium, indium or combinations thereof.

6. The method of claim 1, wherein the group III/V layer is a ternary layer.

7. The method of claim 1, wherein the group III/V layer is less than 50nm thick.

8. A method of forming a layer, comprising:

cleaning an exposed surface of a substrate;

depositing a group III nucleation layer over the exposed surface at a first temperature, the group III nucleation layer being free of a group V element;

depositing a binary or ternary group III/V layer on the group III nucleation layer at a second temperature; and

annealing the binary or ternary group III/V layer.

9. The method of claim 8, wherein the group III nucleation layer is deposited to a thickness of between 10 nm and 30 nm.

10. The method of claim 8, wherein the second temperature is higher than the first temperature.

11. The method of claim 8, further comprising depositing one or more additional binary or ternary group III/V layers and annealing the additional binary or ternary group III/V layers.

12. The method of claim 11, wherein at least one of the additional binary or ternary group III/V layers comprises a group III element or a group V element which is different from the previous binary or ternary group III/V layer.

13. The method of claim 12, wherein the second temperature is maintained during the deposition of the one or more additional binary or ternary group III/V layers.

14. The method of claim 8, wherein the binary or ternary group III/V layer is annealed at a temperature between about 400°

C. and about 600°

C.

15. A device, comprising:

a silicon substrate comprising;

a first surface; and

a second surface disposed opposite the first surface;

a group III nucleation layer disposed on the first surface of the silicon substrate, wherein the group III nucleation layer being free of a group V element; and

a group III/V buffer layer on top of the group III nucleation layer, wherein the combined nucleation layer and the group III/V buffer layer are from 50 Å

to 300 Å

thick.

16. The device of claim 15, further comprising one or more binary or ternary group III/V layers formed on the group III/V buffer layer.

17. The device of claim 16, wherein the one or more binary or ternary group III/V layers are composed of the same group III or the same group V element as the group III/V buffer layer.

18. The device of claim 15, wherein the group III nucleation layer and the group III/V buffer layer comprise aluminum, gallium, indium or combinations thereof.

19. The device of claim 15, wherein the group III/V buffer layer comprises phosphorus, arsenic or combinations thereof.

20. The device of claim 15, wherein the group III/V buffer layer is a binary layer.