Vertical transport FET devices with uniform bottom spacer

• US 9,799,749 B1
• Filed: 08/18/2016
• Issued: 10/24/2017
• Est. Priority Date: 08/18/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bi, Zhenxing, Cheng, Kangguo, Li, Juntao, Miao, Xin
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): Joy, Jeremy
• Application Number:
  US15/240,056
• Time in Patent Office: 432 Days
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

Methods of fabrication and semiconductor structures includes vertical transport field effect transistors (VTFETs) having a uniform bottom spacer layer between different pattern density regions. The bottom spacer layer can be deposited by plasma vapor deposition.

Claims

1. A method for forming a semiconductor device, the method comprising:

conformally depositing an oxide liner layer onto a semiconductor substrate comprising an isolated fin region and/or a dense fin region, wherein the isolated fin region comprises individual vertically oriented fin structures having a hard mask disposed thereon, each one of the individual vertically oriented fin structures coupled to an individual bottom electrode formed in the semiconductor substrate, and wherein the dense fin region comprises a plurality of vertically oriented fin structures coupled to a shared bottom electrode formed in the semiconductor substrate and the hard mask disposed thereon;

depositing a bottom spacer layer onto the semiconductor substrate, wherein depositing the bottom spacer layer comprises a plasma vapor deposition process, and wherein the bottom spacer layer between the vertically oriented fin structures is at a height greater than the bottom spacer layer in an open region between isolated fin regions and/or dense fin regions;

conformally depositing a second liner layer onto the semiconductor substrate;

forming a planar flowable oxide layer on the semiconductor substrate to a top surface of the vertically oriented fin structures;

removing a portion of the flowable oxide layer to the second liner layer between vertically oriented fin structures in the isolated fin region and/or the dense fin region, thereby exposing the second liner layer about portions of the sidewalls, between vertically oriented fin structures, and on the top surfaces of the vertically oriented fin structures in the isolated fin region and/or the dense fin region;

removing the exposed second liner layer from the sidewalls, between vertically oriented fin structures, and the top surfaces of the vertically oriented fin structures in the isolated fin region and/or the dense fin region; and

non-selectively removing a remaining portion of the flowable oxide, a portion of the bottom spacer layer between the vertically oriented fin structures, and the second liner layer stopping on the bottom spacer layer within the open region, wherein a thickness of the bottom spacer layer is equal in the open region and between the vertically oriented fin structures in the isolated fin region and/or the dense fin region.

2. The method of claim 1, wherein the bottom spacer layer comprises a carbon doped oxide, a nitride, an oxynitride, or combinations thereof.

3. The method of claim 1, wherein the bottom spacer layer is SiBCN.

4. The method of claim 1, wherein conformally depositing an oxide liner layer comprises an atomic layer deposition process.

5. The method of claim 1, wherein the oxide liner layer is silicon dioxide.

6. The method of claim 1, wherein non-selectively removing the remaining portion of the flowable oxide and the second liner layer comprises a reaction ion etch process.

7. The method of claim 1, wherein removing the remaining portion of the flowable oxide and the second liner layer comprises a gas cluster ion beam process.

8. The method of claim 1, wherein the second liner layer is a nitride.

9. The method of claim 1, further comprising removing the hard mask, forming a gate on the bottom spacer layer adjacent the vertically oriented fin structures;

forming a top spacer on the gate; and

forming top electrodes onto each one of the individual vertically oriented fin structures coupled to the individual bottom electrode to form the isolated fin region, and forming a shared top electrode onto the plurality of vertically oriented fin structures coupled to the shared bottom electrode.

10. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate comprising vertically oriented fin structures at different pattern density regions, the vertically oriented fin structures defining an isolated fin region and/or a dense fin region, wherein the vertically oriented fin structures in the isolated fin region are each coupled to an individual bottom electrode, and wherein the vertically oriented fin structures in the dense fin region are each coupled to an shared bottom electrode, the vertically oriented fins structures including a hard mask disposed thereon;

conformally depositing an oxide liner layer onto a semiconductor substrate;

depositing a bottom spacer layer onto a bottom surface of the semiconductor substrate, wherein depositing the bottom spacer layer comprises a plasma vapor deposition process, wherein the bottom spacer layer between the vertically oriented fin structures is at a height greater than the bottom spacer layer in an open region between isolated fin regions and/or dense fin regions, and wherein the bottom spacer layer is a low k dielectric material;

conformally depositing a second liner layer onto the semiconductor substrate;

forming a planar flowable oxide layer on the semiconductor substrate to the second liner layer on top surfaces of the vertically oriented fin structures;

removing a portion of the flowable oxide layer to the second liner layer between the vertically oriented fin structures, thereby exposing the second liner layer about portions of the sidewalls, between the vertically oriented fin structures, and the top surfaces of the vertically oriented fin structures;

isotropically etching the exposed second liner layer from the sidewalls, between the vertically oriented fin structures, and the top surfaces of the vertically oriented fin structures, wherein removing the second liner layer between the vertically oriented fin structures exposes the bottom spacer layer therebetween; and

non-selectively removing a remaining portion of the flowable oxide and the second liner layer stopping on the bottom spacer layer within an open region, wherein stopping on the bottom spacer layer within the open region removes a portion of the bottom spacer layer between the vertically oriented fin structures such that a thickness of the bottom spacer layer is equal in the open region and between the vertically oriented fin structures at the different pattern densities.

11. The method of claim 10, wherein conformally depositing the oxide liner layer onto the semiconductor substrate comprises atomic layer deposition.

12. The method of claim 10, wherein the bottom spacer layer is SiBCN.

13. The method of claim 10, wherein the second liner layer is a nitride.

14. The method of claim 10, wherein removing the remaining portion of the flowable oxide and the second liner layer comprises a non-selective reaction ion etch process or a selective gas cluster ion beam process.

15. The method of claim 10, further comprising removing the hard mask, forming a gate on the bottom spacer layer adjacent the vertically oriented fin structures;

forming a top spacer on the gate; and

forming top electrodes onto each one of the individual vertically oriented fin structures coupled to the individual bottom electrode to form the isolated fin region, and forming a shared top electrode onto the plurality of vertically oriented fin structures coupled to the shared bottom electrode.