Printable inorganic semiconductor structures

• US 9,799,794 B2
• Filed: 03/31/2017
• Issued: 10/24/2017
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: X Display Company Technology Limited (Sensinnovat BVBA)
• Original Assignee: X-Celeprint Limited
• Inventors: Bower, Christopher, Meitl, Matthew, Gomez, David, Prevatte, Jr., Carl, Bonafede, Salvatore
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/476,703
• Publication Number:
  US 20170207364A1
• Time in Patent Office: 207 Days
• Field of Search: 257 98, 438 27, 438455
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68322 Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2221/68381 Details of chemical or physical process used for separating the auxiliary support from a device or wafer
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 2933/0033 relating to semiconductor body packages
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/26 Materials of the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/36 characterised by the electrodes
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

The present invention provides structures and methods that enable the construction of micro-LED chiplets formed on a sapphire substrate that can be micro-transfer printed. Such printed structures enable low-cost, high-performance arrays of electrically connected micro-LEDs useful, for example, in display systems. Furthermore, in an embodiment, the electrical contacts for printed LEDs are electrically interconnected in a single set of process steps. In certain embodiments, formation of the printable micro devices begins while the semiconductor structure remains on a substrate. After partially forming the printable micro devices, a handle substrate is attached to the system opposite the substrate such that the system is secured to the handle substrate. The substrate may then be removed and formation of the semiconductor structures is completed. Upon completion, the printable micro devices may be micro transfer printed to a destination substrate.

Claims

1. A method of making an inorganic semiconductor structure suitable for micro-transfer printing, comprising:

providing a source substrate;

forming a semiconductor layer on the source substrate, wherein the semiconductor layer has a first side and a second side opposite the first side and adjacent to the substrate;

removing a portion of the semiconductor layer to form a cantilever extension;

forming a first electrical contact on the semiconductor layer;

forming a second electrical contact on the cantilever extension;

removing a portion of the semiconductor layer surrounding each pair of first and second electrical contact to form a trench surrounding a semiconductor element made from the semiconductor layer, the semiconductor element having a substrate side in contact with the source substrate and a handle side opposite the substrate side;

providing a sacrificial layer covering the first and second electrical contacts and covering at least a portion of the handle side of the semiconductor element and filling a portion of the trench;

providing an interlayer over the sacrificial layer, the interlayer having different chemical selectivity than the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at the base of the trench to form an anchor;

adhering the interlayer to a handle substrate;

removing the source substrate to expose the substrate side of the semiconductor element;

optionally forming a tether bridging the exposed substrate side of the semiconductor element to the anchor; and

removing the sacrificial layer, thereby forming a printable semiconductor structure partially released from the handle substrate and physically secured to the anchor by the tether.

2. The method of claim 1, wherein the tether comprises a notch, the notch providing a point of fracture for a releasable micro object when retrieved by a transfer element.

3. The method of claim 1, wherein the tether is a narrow shaped tether having a width of 10 μ

m to 40 μ

m.

4. The method of claim 1, wherein the source substrate is a sapphire substrate.

5. The method of claim 1, wherein the semiconductor layer comprises GaN and/or doped GaN.

6. The method of claim 1, wherein the semiconductor layer comprises multiple sub-layers.

7. The method of claim 1, wherein the trench extends through the semiconductor layer to the source substrate.

8. The method of claim 1, wherein the trench extends partially into the semiconductor layer such that a portion of the semiconductor layer forms an ablation layer between the semiconductor element and the source substrate.

9. The method of claim 1, wherein the semiconductor element, the first electrical contact, and the second electrical contact form a diode, a laser, or a light-emitting diode.

10. The method of claim 1, comprising one or more additional electrical contacts, wherein the semiconductor element, the first electrical contact, and the second electrical contact and the one or more additional electrical contacts form a transistor and integrated circuit.

11. The method of claim 1, wherein the first electrical contact has a different thickness than the second electrical contact.

12. The method of claim 1, wherein the first electrical contact and the second electrical contact extend to a common distance from a surface of the semiconductor element.

13. An inorganic semiconductor structure comprising:

a semiconductor element surrounded by a trench, the semiconductor element having a substrate side and a handle side opposite the substrate side;

a first electrical contact on the handle side of the semiconductor element;

a second electrical contact on the substrate side of the semiconductor element;

a sacrificial layer covering the first electrical contact and covering the handle side of at least a portion of the semiconductor element and filling a portion of the trench;

an interlayer formed over the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at a base of the trench to form an anchor;

a handle substrate adhered to the interlayer, wherein at least a portion of the interlayer is between the handle substrate and the sacrificial layer; and

a tether bridging the substrate side of the semiconductor element to the anchor, thereby physically securing the semiconductor element to the anchor.

14. The structure of claim 13, wherein the tether comprises a notch, the notch providing a point of fracture for a releasable micro object when retrieved by a transfer element.

15. The structure of claim 13, wherein the tether is a narrow shaped tether.

16. The structure of claim 13, wherein the source substrate is a sapphire substrate.

17. The structure of claim 13, wherein the semiconductor layer comprises GaN and/or doped GaN.

18. The structure of claim 13, wherein the trench extends through the semiconductor layer to the source substrate.

19. The structure of claim 13, wherein the trench extends partially into the semiconductor layer such that a portion of the semiconductor layer forms an ablation layer between the semiconductor element and the source substrate.

20. An array of inorganic semiconductor structures comprising:

a source substrate;

a plurality of semiconductor elements, each surrounded by a trench of a plurality of trenches and having a substrate side in contact with the source substrate and a handle side opposite the substrate side;

a plurality of first metal contacts, each first metal contract in electrical contact with one of the semiconductor elements of the plurality of semiconductor elements on the handle side;

a plurality of second metal contacts, each second electrical contract in electrical contact with one of the semiconductor elements of the plurality of semiconductor elements on the substrate side;

a sacrificial layer covering at least a portion of each of the semiconductor elements and covering the plurality of first metal contacts and filling a portion of the plurality of trenches;

an interlayer formed over the sacrificial layer, wherein a portion of the interlayer contacts the source substrate at a base of at least portion of the plurality of trenches to form a plurality of anchors;

a handle substrate adhered to the interlayer, wherein at least a portion of the interlayer is between the handle substrate and the sacrificial layer; and

a plurality of tethers, each respective tether bridging the substrate side of one of the semiconductor elements of the plurality of semiconductor elements to one of the anchors of the plurality of anchors.