Moving-sum charge pump

• US 9,800,143 B2
• Filed: 09/09/2016
• Issued: 10/24/2017
• Est. Priority Date: 03/03/2016
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Wu, Xiao, Blaauw, David Theodore, Sylvester, Dennis Michael Chen
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US15/261,387
• Publication Number:
  US 20170257024A1
• Time in Patent Office: 410 Days
• Field of Search: 327536, 363 59- 60
• CPC Class Codes: H02J 2300/24 of photovoltaic origin
• CPC Class Codes: H02J 3/381 Dispersed generators
• CPC Class Codes: H02J 3/466 Scheduling the operation of the generators, e.g. connecting or disconnecting generators to meet a given demand
• CPC Class Codes: H02J 50/001 Energy harvesting or scavenging
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices
• CPC Class Codes: H02J 7/35 with light sensitive cells
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: Y02E 10/56 Power conversion systems, e.g. maximum power point trackers

Abstract

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases. The integrated circuit may include a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases. Each multiplexer may provide a selected voltage from the multiple sets of voltages based on a conversion ratio. The integrated circuit may include a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

Claims

1. An integrated circuit, comprising:

a charge pump stage having multiple charge storage elements arranged to provide multiple sets of voltages in alternating phases;

a voltage multiplexing stage having multiple multiplexers arranged to receive the multiple sets of voltages in the alternating phases, each multiplexer providing a selected voltage from the multiple sets of voltages based on a conversion ratio; and

a voltage summing stage having multiple sampling charge storage elements arranged to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

2. The integrated circuit of claim 1, wherein the charge pump stage receives an input voltage, and wherein each charge storage element receives the input voltage and provides a different multiple of the input voltage.

3. The integrated circuit of claim 1, wherein the multiple charge storage elements are arranged in parallel to provide the multiple sets of voltages in the alternating phases, and wherein the multiple sets of voltages comprise one or more combinations of voltages from the multiple charge storage elements.

4. The integrated circuit of claim 1, wherein the alternating phases include a first phase and a second phase, wherein the second phase is different than the first phase, wherein the second phase is alternated with the first phase, and wherein the second phase is provided after the first phase.

5. The integrated circuit of claim 1, wherein the charge pump stage comprises a first plurality of switching components, wherein the multiple sets of voltages include a first set of voltages and a second set of voltages, wherein the alternating phases include a first phase and a second phase, and wherein the first and second sets of voltages are provided in the alternating phases by switching between the first and second phases with the first plurality of switching components.

6. The integrated circuit of claim 1, wherein the multiple multiplexers are arranged in parallel to separately receive the multiple sets of voltages in the alternating phases.

7. The integrated circuit of claim 1, wherein the voltage multiplexing stage comprises a second plurality of switching components, wherein the multiple sets of voltages include a first set of voltages and a second set of voltages, wherein the alternating phases include a first phase and a second phase, and wherein the multiple multiplexers are arranged to receive the first and second sets of voltages in the alternating phases by switching between the first and second phases with the second plurality of switching components.

8. The integrated circuit of claim 1, wherein the multiple sampling charge storage elements are arranged in parallel to separately receive the selected voltages from each multiplexer.

9. The integrated circuit of claim 1, wherein the sum comprises a series sum of the selected voltages received from each multiplexer.

10. The integrated circuit of claim 1, wherein the voltage summing stage comprises a third plurality of switching components, and wherein the multiple sampling charge storage elements are arranged to receive the selected voltages from each multiplexer and provide the output voltage as the sum of the selected voltages received from each multiplexer by switching the third plurality of switching components.

11. An integrated circuit, comprising:

a first stage having multiple charge storage elements arranged in parallel to provide first and second combinations of voltages in alternating first and second phases, wherein the first combination of voltages is provided in the first phase and the second combination of voltages is provided in the second phase which is different than the first phase;

a second stage having multiple multiplexers arranged in parallel to receive the first and second sets of voltages in the alternating first and second phases, each multiplexer providing a selected voltage from the first and second sets of voltages based on a conversion ratio; and

a third stage having multiple sampling charge storage elements arranged in parallel to receive the selected voltages from each multiplexer and provide an output voltage as a sum of the selected voltages received from each multiplexer.

12. The integrated circuit of claim 11, wherein the first stage receives an input voltage, and wherein each charge storage element receives the input voltage and provides a different multiple of the input voltage.

13. The integrated circuit of claim 11, wherein the multiple charge storage elements include a first set of charge storage elements arranged in a first chain and a second set of charge storage elements arranged in a second chain that is different from the first set of charge storage elements.

14. The integrated circuit of claim 13, wherein the first set of charge storage elements provides the first combination of voltages in the first phase, and wherein the second set of charge storage elements provides the second combination of voltages in the second phase.

15. The integrated circuit of claim 14, wherein each multiplexer receives the first combination of voltages from the first set of charge storage elements in the first phase, and wherein each multiplexer receives the second combination of voltages from the second set of charge storage elements in the second phase.

16. The integrated circuit of claim 11, wherein the sum comprises a series sum of the selected voltages received from each multiplexer.

17. The integrated circuit of claim 11, wherein the first stage comprises a charge pump stage having a first plurality of switching components, and wherein the first and second combinations of voltages are provided in the alternating phases by switching between the first and second phases with the first plurality of switching components.

18. The integrated circuit of claim 11, wherein the second stage comprises a voltage multiplexing stage having a second plurality of switching components, and wherein the multiple multiplexers are arranged in parallel to receive the first and second combinations of voltages in the alternating phases by switching between the first and second phases with the second plurality of switching components.

19. The integrated circuit of claim 11, wherein the third stage comprises a voltage summing stage having a third plurality of switching components, and wherein the multiple sampling charge storage elements are arranged to receive the selected voltages from each multiplexer and provide the output voltage as a series sum of the selected voltages received from each multiplexer by switching the third plurality of switching components.

20. A method, comprising:

arranging multiple sets of charge storage elements in parallel to provide multiple sets of voltages in alternating phases;

arranging multiple multiplexers in parallel to receive the multiple sets of voltages in the alternating phases, wherein each multiplexer provides a selected voltage from the multiple sets of voltages based on a conversion ratio; and

arranging multiple sampling charge storage elements in parallel to receive the selected voltages from each multiplexer, wherein the multiple sampling charge storage elements provide an output voltage as a sum of the selected voltages received from each multiplexer.