Data processing device and driving method thereof

• US 9,800,247 B2
• Filed: 06/14/2016
• Issued: 10/24/2017
• Est. Priority Date: 01/17/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): LE, DON P
• Application Number:
  US15/181,646
• Publication Number:
  US 20160285457A1
• Time in Patent Office: 497 Days
• Field of Search: 326 38, 326 41
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 9/445 Program loading or initiating bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 19/1735 by wiring, e.g. uncommitted logic arrays
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/1776 for memories

Abstract

In a processor or the like including a reconfigurable (RC) circuit, the RC circuit is used to form a test circuit to test a core, a cache memory, or the like, and then part of the RC circuit is used as an auxiliary cache memory. When a memory can store data after stop of power supply, a startup routine program (SRP) of the processor can be stored therein. For example, after the test, an SRP is loaded to a memory in the RC circuit from an external ROM or the like, and when power is resupplied to the processor, a startup operation is performed using the loaded SRP. When the processor is in a normal operation state, this memory is used as an auxiliary cache memory and the SRP is overwritten. The SRP is loaded to the memory again at the end of use of the processor.

Claims

1. A data processing device comprising:

a processing unit; and

a reconfigurable circuit comprising a switch array matrix, and a logic circuit,

wherein the switch array matrix comprises a plurality of programmable switches,

wherein each of the plurality of programmable switches is configured to make an electrical connection and an electrical disconnection between two wirings, and

wherein the reconfigurable circuit is configured to work as a test circuit when a test for the processing unit is performed, and to work as a nonvolatile memory storing a startup routine program used when the processing unit starts up.

2. The data processing device according to claim 1,

wherein the logic circuit comprising a switch,

wherein signals are configured to be input to the logic circuit via a plurality of wirings, and

wherein an output signal of the logic circuit is configured to be exported via the switch.

3. The data processing device according to claim 2, wherein the switch is a tri-state buffer.

4. The data processing device according to claim 1, wherein the reconfigurable circuit is configured to work as a cache memory for the processing unit.

5. The data processing device according to claim 4, wherein the cache memory is used as a tag memory.

6. A method for driving the data processing device according to claim 1, comprising:

reconfiguring the reconfigurable circuit as the test circuit;

performing the test by using the test circuit; and

storing the startup routine program after the test.

7. A data processing device comprising:

a processing unit; and

a reconfigurable circuit comprising a switch array matrix, and a logic circuit,

wherein the switch array matrix comprises a plurality of programmable switches,

wherein each of the plurality of programmable switches is configured to make an electrical connection and an electrical disconnection between two wirings,

wherein the reconfigurable circuit is configured to work as a test circuit when a test for the processing unit is performed, and

wherein the data processing device is configured to execute following steps after starting a power supply to the reconfigurable circuit;

loading a startup routine program into the processing unit from the reconfigurable circuit; and

starting up the processing unit by using the startup routine program stored in the processing unit.

8. The data processing device according to claim 7,

wherein the logic circuit comprising a switch,

wherein signals are configured to be input to the logic circuit via a plurality of wirings, and

wherein an output signal of the logic circuit is configured to be exported via the switch.

9. The data processing device according to claim 8, wherein the switch is a tri-state buffer.

10. The data processing device according to claim 7, wherein the reconfigurable circuit is configured to work as a cache memory for the processing unit.

11. The data processing device according to claim 10, wherein the cache memory is used as a tag memory.

12. A method for driving the data processing device according to claim 7, comprising:

reconfiguring the reconfigurable circuit as the test circuit;

performing the test by using the test circuit; and

storing the startup routine program after the test.

13. A data processing device comprising:

a processing unit; and

a reconfigurable circuit comprising a switch array matrix, and a logic circuit,

wherein the data processing device is configured to execute following steps;

starting a power supply to the reconfigurable circuit followed by loading a startup routine program into the processing unit from the reconfigurable circuit;

starting up the processing unit by using the startup routine program stored in the processing unit

reconfiguring the reconfigurable circuit as a test circuit; and

performing a test for the processing unit by using the test circuit.

14. The data processing device according to claim 13,

wherein the logic circuit comprising a switch,

wherein signals are configured to be input to the logic circuit via a plurality of wirings, and

wherein an output signal of the logic circuit is configured to be exported via the switch.

15. The data processing device according to claim 14, wherein the switch is a tri-state buffer.

16. The data processing device according to claim 13, wherein the reconfigurable circuit is configured to work as a cache memory for the processing unit.

17. The data processing device according to claim 16, wherein the cache memory is used as a tag memory.

18. A method for driving the data processing device according to claim 13, comprising:

reconfiguring the reconfigurable circuit as the test circuit;

performing the test by using the test circuit; and

storing the startup routine program after the test.