Frequency and time domain streaming receiver
First Claim
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1. A wideband signal processing receiver system comprising:
- an interface for connecting to an analogue to digital converter (ADC) of a broader signal chain lineup, wherein said interface receives digital data from said ADC;
a field programmable gate array (FPGA) including a microprocessor and instructions executed by said microprocessor for converting said digital data into two digital signal paths; and
a memory and/or high speed bus for storing data from said two digital signal paths;
wherein a first digital signal path includes FPGA circuit logic implementing windowing logic and a fast Fourier transform to convert the digital signal into the frequency domain;
and wherein the fast Fourier transform logic and the windowing logic are dynamically alterable within the FPGA to accommodate different modes of operation for the receiver system.
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Abstract
A wideband signal processing receiver system including an interface for connecting to an analog to digital converter (ADC) of a broader signal chain lineup, wherein the interface receives digital data from the ADC, and a field programmable gate array (FPGA) and associated configuration for converting the digital data into two digital signal paths. The two digital signal paths include a frequency domain path and an optionally decimated time domain path. A memory and/or high speed bus stores or transfers high speed bus/link data from the frequency domain path and the time domain path.
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10 Claims
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1. A wideband signal processing receiver system comprising:
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an interface for connecting to an analogue to digital converter (ADC) of a broader signal chain lineup, wherein said interface receives digital data from said ADC; a field programmable gate array (FPGA) including a microprocessor and instructions executed by said microprocessor for converting said digital data into two digital signal paths; and a memory and/or high speed bus for storing data from said two digital signal paths; wherein a first digital signal path includes FPGA circuit logic implementing windowing logic and a fast Fourier transform to convert the digital signal into the frequency domain; and wherein the fast Fourier transform logic and the windowing logic are dynamically alterable within the FPGA to accommodate different modes of operation for the receiver system. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification