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Mapped FIFO buffering

  • US 9,800,513 B2
  • Filed: 03/24/2015
  • Issued: 10/24/2017
  • Est. Priority Date: 12/20/2010
  • Status: Active Grant
First Claim
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1. A network interface device for connection between a network and a data processing system, the network interface device comprising:

  • a common memory configured to buffer data packets;

    a plurality of ports operable to receive data packets for writing to the common memory;

    a memory manager configured to store information defining a plurality of virtual queues held in the common memory, wherein the memory manager is configured to associate one or more of the virtual queues with each port such that data packets received at a port are written to the one or more virtual queues associated with that port, wherein a linked logical sequence of buffers in said common memory represents each virtual queue; and

    an interface configured to;

    receive from the memory manager an indication of one or more buffers for each linked logical sequence of buffers representing a virtual queue; and

    service the ports and write data packets received at a respective port into the indicated one or more buffers of the linked logical sequence of buffers representing a virtual queue associated with that port.

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