Method for MEMS structure with dual-level structural layer and acoustic port

• US 9,802,815 B2
• Filed: 12/02/2015
• Issued: 10/31/2017
• Est. Priority Date: 02/27/2013
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Daneman, Michael Julian, Chan, Mei-Lin, Lim, Martin, Assaderaghi, Fariboz, Ata, Erhan Polatkan
• Primary Examiner(s): Moore, Whitney T
• Assistant Examiner(s): Assouman, Herve
• Application Number:
  US14/957,562
• Publication Number:
  US 20160083247A1
• Time in Patent Office: 699 Days
• Field of Search: 257414-419, 438 50- 53
• CPC Class Codes: B81B 2201/0257 Microphones or microspeakers
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/012 the micromechanical device and the control or processing electronics being separate parts in the same package
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/112 Depositing an anti-stiction or passivation coating, e.g. on the elastic or moving parts
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface

Abstract

A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer.

Claims

1. A method for fabricating a MEMS device comprising:

forming a first silicon wafer with a first cavity;

after forming the forming the first silicon wafer, forming a first oxide layer lining the first cavity;

forming a second silicon wafer, the second silicon wafer comprising a handle wafer, a device wafer, and oxide disposed between the second silicon wafer and the handle wafer;

bonding the first silicon wafer to the second silicon wafer;

depositing a second oxide layer on top of the second silicon wafer;

removing the handle wafer of the second silicon wafer leaving the second oxide layer on the second silicon wafer;

patterning the second oxide layer;

depositing a polysilicon layer on the patterned second oxide layer;

planarizing the polysilicon layer and stopping the planarizing at the second oxide layer;

removing the second oxide layer;

depositing and patterning a conductive layer; and

bonding the second silicon wafer with an electrical connection.

2. The method for fabricating a MEMS device, as recited in claim 1, further including opening a port in the second silicon wafer.

3. The method for fabricating a MEMS device, as recited in claim 1, further including opening a port in the first silicon wafer.

4. The method for fabricating a MEMS device, as recited in claim 1, wherein the second silicon layer includes a dielectric layer and forming cavities in the dielectric layer.

5. The method for fabricating a MEMS device, as recited in claim 1, wherein the second silicon wafer is a CMOS layer.

6. A method for fabricating a MEMS device comprising:

forming a silicon-on-insulator (SOI) wafer with a cavity, the SOI wafer comprising a handle layer, a device layer and oxide formed between the handle layer and the device layer;

depositing a first oxide layer on the SOI wafer and patterning the deposited first oxide layer;

after depositing the first oxide layer, depositing a second oxide layer on top of the cavity thereby lining the cavity with the oxide layer;

depositing polysilicon on the patterned first oxide layer;

depositing a conductive layer on the polysilicon;

patterning and etching the polysilicon and the conductive layer;

further etching the device layer;

removing the patterned first oxide layer thereby forming a MEMS substrate;

bonding the MEMS substrate to the CMOS wafer, the CMOS wafer having at least one metal layer;

forming an electrical connection between the MEMS substrate and the at least one metal layer;

thinning the handle layer;

patterning the handle layer; and

removing the first oxide layer deposited on the SOI wafer.

7. The method for fabricating a MEMS device, as recited in claim 6, further including bonding the MEMS substrate to a silicon cap wafer with cavities.

8. The method for fabricating a MEMS device, as recited in claim 7, further including an opening port in the silicon cap wafer.

9. The method for fabricating a MEMS device, as recited in claim 6, further including opening a port in the CMOS wafer.