Reaction chamber passivation and selective deposition of metallic films

• US 9,803,277 B1
• Filed: 06/08/2016
• Issued: 10/31/2017
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Longrie, Delphine, Niskanen, Antti Juhani, Wang, Han, Xie, Qi, Maes, Jan Willem, Chen, Shang, Watarai, Toshiharu, Onuma, Takahiro, Ishikawa, Dai, Namba, Kunitoshi
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US15/177,195
• Time in Patent Office: 510 Days
• CPC Class Codes: C23C 16/02 Pretreatment of the material to be coated C23C16/04 takes precedence
• CPC Class Codes: C23C 16/06 characterised by the deposition of metallic material
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/4404 Coatings or surface treatment on the inside of the reaction chamber or on parts thereof
• CPC Class Codes: C23C 16/4405 Cleaning of reactor or parts inside the reactor by using reactive gases
• CPC Class Codes: C23C 16/45525 Atomic layer deposition [ALD]
• CPC Class Codes: C23C 16/45536 Use of plasma, radiation or electromagnetic fields
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material

Abstract

Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

Claims

1. A process for passivating a reaction chamber prior to conducting a selective deposition process therein, the process comprising:

providing a reaction chamber that does not comprise a wafer;

depositing a passivation layer on an interior surface of the reaction chamber, wherein the interior surface may be exposed to a precursor during a subsequent selective deposition process;

providing at least one wafer comprising a first metallic surface and a second surface comprising silicon into the reaction chamber;

performing a selective deposition process on the at least one wafer within the reaction chamber, wherein the selective deposition process comprises at least one selective deposition cycle; and

repeating the depositing a passivation layer step after a number of selective deposition cycles have been performed.

2. The process of claim 1, further comprising subjecting an interior surface of the reaction chamber to an etch process prior to depositing a passivation layer on an interior surface of the reaction chamber.

3. The process of claim 1, wherein no substrate or wafer is present in the reaction chamber during the deposition of the passivation layer on the interior surface of the reaction chamber.

4. The process of claim 1, wherein the passivation layer is deposited by a vapor deposition process.

5. The process of claim 4, wherein the passivation layer is deposited by an atomic layer deposition (ALD) process.

6. The process of claim 5, wherein the passivation layer is deposited by a plasma enhanced atomic layer deposition (PEALD) process.

7. The process of claim 6, wherein the passivation layer is formed by alternately and sequentially exposing the reaction chamber to a first precursor comprising disilane and a second precursor comprising atomic nitrogen, nitrogen radicals, or nitrogen plasma and atomic hydrogen, hydrogen radicals or hydrogen plasma.

8. The process of claim 4, wherein the passivation layer is deposited by a chemical vapor deposition (CVD) process.

9. The process of claim 8, wherein the passivation layer is deposited by a plasma enhanced CVD (PECVD) process.

10. The process of claim 1, wherein the passivation layer comprises SiN.

11. The process of claim 1, wherein the passivation layer does not comprise pure metal or pure silicon.

12. The process of claim 1, wherein the passivation layer has a thickness of from about 5 nm to about 500 nm.

13. The process of claim 1, wherein the selective deposition process has a selectivity of greater than about 50%.

14. The process of claim 1, wherein the selective deposition process has a selectivity of greater than about 90%.

15. A process for passivating a reaction chamber, the process comprising:

providing a reaction chamber that does not comprise a wafer;

depositing a passivation layer on an interior surface of the reaction chamber;

providing at least one wafer comprising a first metallic surface and a second surface comprising silicon into the reaction chamber;

performing a selective deposition process on the at least one wafer within the reaction chamber,

wherein the passivation layer is formed by oxidizing a metal deposited on an interior surface of the reaction chamber.

16. The process of claim 15, wherein the metal is deposited on the interior surface of the reaction chamber by selective deposition process.

17. The process of claim 16, wherein the metal comprises tungsten.

18. A process for passivating a reaction chamber prior to conducting a selective deposition process therein, the process comprising:

providing a reaction chamber that does not comprise a wafer;

depositing a passivation layer on an interior surface of the reaction chamber, wherein the interior surface may be exposed to a precursor during a subsequent selective deposition process;

providing at least one wafer comprising a first metallic surface and a second surface comprising silicon into the reaction chamber;

performing a selective deposition process on the at least one wafer within the reaction chamber, wherein the selective deposition process comprises at least one selective deposition cycle; and

intermittently repeating the depositing a passivation layer step during the selective deposition process.

19. The process of claim 18, wherein the passivation layer comprises SiN.