Thread context preservation in a multithreading computer system

• US 9,804,846 B2
• Filed: 03/27/2014
• Issued: 10/31/2017
• Est. Priority Date: 03/27/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bradbury, Jonathan D., Busaba, Fadi Y., Farrell, Mark S., Gainey, Jr., Charles W., Greiner, Dan F., Heller, Lisa Cranton, Kubala, Jeffrey P., Osisek, Damian L., Schmidt, Donald W., Slegel, Timothy J.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US14/226,895
• Publication Number:
  US 20150277919A1
• Time in Patent Office: 1,314 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/463 Program control block organisation

Abstract

According to one aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads. The computer system also includes a multithreading facility configured to control utilization of the configuration to perform a method. Based on determining, by the core in the MT mode, that MT is to be disabled, the MT mode switches to the ST mode, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed.

Claims

1. A computer system, comprising:

a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core; and

a multithreading facility configured to control utilization of the configuration to perform a method comprising;

based on determining, by the core in the MT mode, that MT is to be disabled in response to a reset or a deactivation, switching from the MT mode to the ST mode, wherein the primary thread of the MT mode is maintained as the primary thread of the ST mode, wherein a thread context comprising program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs by shifting an expanded address value comprising a core address value and a thread address value to eliminate the thread address value based on a requested maximum thread identifier; and

based on the switching, performing any one of clearing the program accessible register values or retaining the program accessible register values.

2. The computer system according to claim 1, wherein the determining that MT is to be disabled further comprises:

based on a non-clearing operation, determining that the program accessible register values are to be retained; and

based on a clearing operation, determining that the program accessible registers are to be cleared.

3. The computer system according to claim 1, wherein the thread context comprises:

program general purpose registers, floating-point registers, control registers, access registers, a prefix register, and a time of day (TOD) programmable register.

4. The computer system according to claim 3, wherein the thread context further comprises a program status word for each thread.

5. The computer system according to claim 4, wherein a last-set program-specified maximum thread identifier is set based on a last successfully executed signal processor instruction.

6. The computer system according to claim 1, wherein based on switching to the MT mode, the program accessible register values are made accessible to programs based on corresponding secondary threads being re-enabled.

7. The computer system according to claim 1, wherein a primary thread context comprising program accessible register values and program counter values of the primary thread is accessible to programs in both the ST mode and the MT mode.

8. The computer system according to claim 1, wherein the thread context is maintained in any of:

a state-description block, a satellite block anchored to the state-description block in memory, or a context register.

9. A computer program product for thread context preservation in a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core, the computer program product comprising:

a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a signal, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising;

based on determining, by the core in the MT mode, that MT is to be disabled in response to a reset or a deactivation, switching from the MT mode to the ST mode, wherein the primary thread of the MT mode is maintained as the primary thread of the ST mode, wherein a thread context comprising program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs by shifting an expanded address value comprising a core address value and a thread address value to eliminate the thread address value based on a requested maximum thread identifier; and

based on the switching, performing any one of clearing the program accessible register values or retaining the program accessible register values.

10. The computer program product according to claim 9, wherein the determining that MT is to be disabled further comprises:

based on a non-clearing operation, determining that the program accessible register values are to be retained; and

based on a clearing operation, determining that the program accessible registers are to be cleared.

11. The computer program product according to claim 9, wherein the thread context comprises:

program general purpose registers, floating-point registers, control registers, access registers, a prefix register, and a time of day (TOD) programmable register.

12. The computer program product according to claim 11, wherein the thread context further comprises a program status word for each thread.

13. The computer program product according to claim 12, wherein a last-set program-specified maximum thread identifier is set based on a last successfully executed signal processor instruction.

14. The computer program product according to claim 9, wherein based on switching to the MT mode, the program accessible register values are made accessible to programs based on corresponding secondary threads being re-enabled.

15. The computer program product according to claim 9, wherein a primary thread context comprising program accessible register values and program counter values of the primary thread is accessible to programs in both the ST mode and the MT mode.

16. The computer program product according to claim 9, wherein the thread context is maintained in any of:

a state-description block, a satellite block anchored to the state-description block in memory, or a context register.