Thread context preservation in a multithreading computer system
First Claim
1. A computer implemented method for thread context preservation in a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core, the method comprising:
- based on determining, by the core in the MT mode, that MT is to be disabled in response to a reset or a deactivation, switching from the MT mode to the ST mode, wherein the primary thread of the MT mode is maintained as the primary thread of the ST mode, wherein a thread context comprising program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs by shifting an expanded address value comprising a core address value and a thread address value to eliminate the thread address value based on a requested maximum thread identifier; and
based on the switching, performing any one of clearing the program accessible register values or retaining the program accessible register values.
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Abstract
According to one aspect, a computer-implemented method for thread context preservation in a configuration including a core configurable between a single thread (ST) mode and a multithreading (MT) mode is provided. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. Based on determining, by the core in the MT mode, that MT is to be disabled, switching from the MT mode to the ST mode is performed, where the primary thread of the MT mode is maintained as the primary thread of the ST mode. A thread context including program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs. Based on the switching, any one of clearing the program accessible register values or retaining the program accessible register values is performed.
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Citations
8 Claims
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1. A computer implemented method for thread context preservation in a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core, the method comprising:
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based on determining, by the core in the MT mode, that MT is to be disabled in response to a reset or a deactivation, switching from the MT mode to the ST mode, wherein the primary thread of the MT mode is maintained as the primary thread of the ST mode, wherein a thread context comprising program accessible register values and program counter values of the one or more secondary threads is made inaccessible to programs by shifting an expanded address value comprising a core address value and a thread address value to eliminate the thread address value based on a requested maximum thread identifier; and based on the switching, performing any one of clearing the program accessible register values or retaining the program accessible register values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification