Method and system for driving a light emitting device display

• US 9,805,653 B2
• Filed: 04/05/2016
• Issued: 10/31/2017
• Est. Priority Date: 06/08/2005
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Nathan, Arokia, Chaji, Gholamreza
• Primary Examiner(s): Mehmood, Jennifer
• Assistant Examiner(s): Abebe, Sosina
• Application Number:
  US15/090,769
• Publication Number:
  US 20160217737A1
• Time in Patent Office: 574 Days
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2310/0216 Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
• CPC Class Codes: G09G 2310/0218 with collection of electrodes in groups for n-dimensional addressing
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element

Abstract

A method and system for driving a light emitting device display is provided. The system provides a timing schedule which increases accuracy in the display. The system may provide the timing schedule by which an operation cycle is implemented consecutively in a group of rows. The system may provide the timing schedule by which an aging factor is used for a plurality of frames.

Claims

1. A method of driving a display system using a segmented addressing scheme, the display system comprising a pixel array including a plurality of pixel circuits divided into a plurality of segments according to the segmented addressing scheme, each of the plurality of segments including pixel circuits in more than one row of the pixel array, each pixel circuit having a light emitting device, a drive transistor for driving the light emitting device to emit light, a capacitor, a first switch transistor connected to a data line for programming the pixel circuit to cause a programming voltage to be stored in the capacitor, and a second switch transistor for generating a threshold voltage of the drive transistor during a generating threshold voltage operation, the method comprising:

simultaneously controlling the second switch transistors in a plurality of pixel circuits in more than one row of the pixel array with shared control signals, each of the plurality of pixel circuits being in a first segment of the plurality of segments, to simultaneously generate the threshold voltages of the drive transistors in the first segment during the generating threshold voltage operation in the plurality of pixel circuits in the first segment without affecting the data line immediately following pre-charging the capacitor to a negative voltage during a compensation voltage generation phase that precedes the generation of the threshold voltage, and

controlling a first switch transistor in a second pixel circuit in a second segment of the plurality of segments to program the second pixel circuit via the data line, independently from controlling the second switch transistors of the plurality of pixel circuits in the first segment.

2. A method as claimed in claim 1, wherein each segment includes a plurality of rows, the controlling the second switch transistors being executed consecutively for each segment in the plurality of segments.

3. A method as claimed in claim 1, further comprising:

subsequently implementing controlling the second switch transistor and controlling the first switch transistor of the first segment, after controlling the second switch transistor and controlling the first switch transistor are carried out in the second segment.

4. A method as claimed in claim 1, wherein the controlling the second switch transistor is carried out in the first segment while the controlling the second switch transistor is carried out in the second segment.

5. A pixel driver for a light emitting device, comprising:

a drive transistor for driving a light emitting device, the drive transistor having a gate terminal, a first terminal, and a second terminal connected to a controllable voltage line;

a first capacitor and a second capacitor, the first and second capacitors being connected to the gate terminal of the drive transistor and the controllable voltage line in series;

a first switch transistor having a gate terminal, a first terminal, and a second terminal, the gate terminal of the first switch transistor being connected to a first select line, the first terminal of the first switch transistor being connected to the first terminal of the drive transistor and the light emitting device, the second terminal of the first switch transistor being connected to the gate terminal of the drive transistor;

a second switch transistor having a gate terminal, a first terminal, and a second terminal, the gate terminal of the second switch transistor being connected to a second select line, the first terminal of the second switch transistor being connected to a data line, the second terminal of the second switch transistor being connected to the first and second capacitors.

6. A pixel driver as claimed in claim 5, comprising:

a third switch transistor having a gate terminal, a first terminal, and a second terminal, the gate terminal of the third switch transistor being connected to the first select line, the first terminal of the third switch transistor being connected to the first and second capacitors, the second terminal of the third switch transistor being connected to the controllable voltage line.

7. A pixel driver for a light emitting device, comprising:

a drive transistor for driving a light emitting device, the drive transistor having a gate terminal, a first terminal and a second terminal, the first terminal of the drive transistor coupled to the light emitting device;

a first capacitor and a second capacitor, the first and second capacitors being connected to the gate terminal of the drive transistor in series;

a first switch transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the first switch transistor being connected to a controlling signal line, the first terminal of the first transistor being connected to the first capacitor, the second terminal of the first switch transistor being connected to the first terminal of the drive transistor;

a second switch transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the second switch transistor being connected to a first select line, the first terminal of the second switch transistor being connected to a data line, the second terminal of the second switch transistor being connected to the first and second capacitors; and

a third switch transistor having a gate terminal, a first terminal and a second terminal, the gate terminal of the third switch transistor being connected to a second select line, the first terminal of the third switch transistor being connected to the first terminal of the drive transistor.

8. A pixel driver as claimed in claim 7, wherein the second capacitor, the second terminal of the third switch transistor, and the second select line are connected to a controllable voltage line.