Memory device, peripheral circuit thereof and single-byte data write method thereof

• US 9,805,776 B2
• Filed: 12/15/2016
• Issued: 10/31/2017
• Est. Priority Date: 01/19/2016
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lin, Yih-Lang
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US15/381,089
• Publication Number:
  US 20170206945A1
• Time in Patent Office: 320 Days
• Field of Search: 36518905
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42328 : with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 41/00 : Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 : characterised by the top-view layout
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell

Abstract

A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a Y decoder, a page buffer, and a write circuit. The write circuit is coupled to a memory array and the page buffer through the Y decoder and receives a byte of program data. The write circuit is based on a memory address corresponding to the program data to receive a plurality of bytes of array data stored in the memory array through the Y decoder, and the read array data is written to page buffer through the Y decoder. Next, the program data is written to the memory array through the write circuit and Y decoder, and the array data is written to the memory array by the page buffer.

Claims

1. A peripheral circuit of a memory device, comprising:

a Y decoder, coupled to a memory array of the memory device;

a page buffer, coupled to the memory array and the Y decoder;

a write circuit, coupled to the memory array and the page buffer through the Y decoder and receiving a byte of a program data; and

a sense amplifier coupled between the Y decoder and the write circuit, reading a plurality of bytes of a array data stored by the memory array through the Y decoder to provide the read array data to the write circuit;

wherein the read array data is based on a memory address corresponding to the program data, the read array data is written to the page buffer through the Y decoder, the program data is written to the memory array through the write circuit and the Y decoder, and the array data is written to the memory array by the page buffer.

2. The peripheral circuit as claimed in claim 1, wherein the memory address comprises a word line address and a bit line address, and the program data and the array data correspond to the same word line address.

3. The peripheral circuit as claimed in claim 2, further comprising a word line decoder which drives the memory array according to the word line address.

4. The peripheral circuit as claimed in claim 1, wherein the memory array comprises a plurality of memory cells and the memory cells corresponding to the memory address and the memory cells corresponding to the array data are erased after the write circuit has written the array data to the page buffer.

5. The peripheral circuit as claimed in claim 1, wherein the Y decoder and the page buffer are coupled to the memory array through a plurality of bit lines.

6. The peripheral circuit as claimed in claim 5, wherein the memory array comprises a plurality of memory cells, the Y decoder comprises a plurality of decoding units and the page buffer comprises a plurality of buffer units, wherein each of the decoding units and each of the buffer units are coupled to the corresponding one of memory cells through the corresponding one of bit lines.

7. The peripheral circuit as claimed in claim 6, wherein each of the buffer units comprises:

a first transmission gate, has a first end coupled to the corresponding bit line, a second end coupled to a internal latch node, a positive control end receiving a page buffer enable signal and a negative control end receiving an inverted page buffer enable signal;

a first inverter, has an input end coupled to the internal latch node and an output end;

a tri-state inverter, has an input end coupled to the output end of the first inverter, and an output end coupled to the internal latch node, wherein the tri-state inverter is controlled by the page buffer enable signal and a Y decode signal.

8. The peripheral circuit as claimed in claim 7, wherein the tri-state inverter comprises:

a first transistor, has a first source/drain receiving a first reference voltage, a first gate receiving the Y decode signal, and a second source/drain;

a second transistor, has a third source/drain coupled to the second source/drain, a second gate coupled to the input end, and a fourth source/drain coupled to the output end;

a third transistor, has a fifth source/drain coupled to the output end, a third gate coupled to the input end and a sixth source/drain;

a fourth transistor, has a seventh source/drain coupled to the sixth source/drain, a fourth gate receiving an inverted Y decode signal, and a eighth source/drain receiving a second reference voltage;

a fifth transistor, has a ninth source/drain receiving the first reference voltage, a fifth gate receiving the page buffer enable signal, and a tenth source/drain coupled to the second source/drain; and

a sixth transistor, has a eleventh source/drain coupled to the sixth source/drain, a sixth gate receiving the inverted page buffer enable signal, and a twelfth source/drain receiving the second reference voltage.

9. The peripheral circuit as claimed in claim 8, wherein the Y decoder is coupled to the write circuit through a plurality of data lines.

10. The peripheral circuit as claimed in claim 9, wherein each of the decoding units comprises:

a second transmission gate, has a first end coupled to the corresponding bit line, a second end coupled to the corresponding data line, a positive control end receiving the Y decode signal and a negative control end receiving the inverted Y decode signal.

11. The peripheral circuit as claimed in claim 9, wherein the write circuit comprises a plurality of write units and each of the write units comprises:

a third transmission gate, has a first end receiving the array data, a second end, a positive control end receiving an inverted data selection signal and a negative control end receiving a data selection signal;

a fourth transmission gate, has a first end receiving the program data, a second end coupled to the second end of the third transmission gate, a positive control end receiving the data selection signal and a negative control end receiving the inverted data selection signal;

a second inverter, has a input end coupled to the second end of the third transmission gate and a output end; and

a third inverter, has a input end coupled to the output end of the second inverter, a output end coupled to the corresponding data line; and

a control end receiving a write enable signal.

12. The peripheral circuit as claimed in claim 1, wherein the memory array and the Y decoder are turned on and the page buffer is turned off when the sense amplifier reads the array data of the memory array, the Y decoder and the page buffer are turned on and the memory array is turned off when the write circuit writes the array data to the page buffer, the memory array, the page buffer and the Y decoder are turned on, when the write circuit writes the program data to the memory array, and the memory array and the page buffer are turned on and the Y decoder is turned off when the array data is written to the memory array by the page buffer.

13. A memory device, comprising:

a memory array; and

a peripheral circuit as claimed in claim 1, coupled to the memory array and receiving a byte of a program data to write the program data to the memory array.

14. A single-byte data write method of a memory device, comprising:

receiving a byte of a program data through a write circuit;

reading a plurality of bytes of a array data stored by a memory array according to a memory address corresponding to the program data through a sense amplifier and a Y decoder and writing the array data to a page buffer through the write circuit and the Y decoder;

writing the program data to the memory array through the write circuit and the Y decoder; and

writing the array data to the memory array through the page buffer.

15. The single-byte data write method as claimed in claim 14, wherein the memory address comprises a word line address and a bit line address and the program data and the array data correspond to the same word line address.

16. The single-byte data write method as claimed in claim 14, wherein the memory array comprises a plurality of memory cells and the single-byte data write method further comprises:

erasing the memory cells corresponding to the memory address and the memory cells corresponding to the array data after the write circuit has write the array data to the page buffer.

17. The single-byte data write method as claimed in claim 14, further comprising:

turning on the memory array and the Y decoder and turning off the page buffer when the sense amplifier reads the array data of the memory array;

turning on the Y decoder and the page buffer and turning off the memory array when the write circuit writes the array data to the page buffer;

turning on the memory array, the page buffer and the Y decoder when the write circuit writes the program data to the memory array; and

turning on the memory array and the page buffer and turning off the Y decoder when the array data is written to the memory array by the page buffer.

18. The single-byte data write method as claimed in claim 14, wherein writing the program data to the memory array through the write circuit and the Y decoder while writing the array data to the memory array through the page buffer.

19. The single-byte data write method as claimed in claim 14, wherein the step of reading the bytes of the array data stored by the memory array according to the memory address corresponding to the program data through the sense amplifier and the Y decoder and writing the array data to a page buffer through the write circuit and the Y decoder comprises:

A) setting a word line address and a bit line address corresponding to the memory address of the program data;

B) increasing the bit line address gradually;

C) reading a byte of the array data in a page of the memory array according to the increased bit line address through the sense amplifier and the Y decoder;

D) writing the read array data into the page buffer through the write circuit and the Y decoder;

E) when the increased bit line address is not corresponded to the last unread array data in the page, repeating the steps B to E, wherein the last unread array data is not corresponded to the bit line address of the memory address; and

F) when the increased bit line address is corresponded to the last unread array data in the page, stopping the reading of the array data.

20. The single-byte data write method as claimed in claim 14, wherein a size of a page in the memory array is M bytes, and the step of reading the bytes of the array data stored by the memory array according to the memory address corresponding to the program data comprises:

counting from 1 to M to generate a count result, wherein M is an integer;

reading a byte of the array data when the count result is smaller than M; and

stopping the reading of the array data when the count result is equal to M.