Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements from such pads

• US 9,805,994 B1
• Filed: 04/04/2016
• Issued: 10/31/2017
• Est. Priority Date: 02/03/2015
• Status: Expired due to Fees

• Current Assignee: PDF Solutions
• Original Assignee: PDF Solutions
• Inventors: Lam, Stephen, Ciplickas, Dennis, Brozek, Tomasz, Cheng, Jeremy, Comensoli, Simone, De, Indranil, Doong, Kelvin, Eisenmann, Hans, Fiscus, Timothy, Haigh, Jonathan, Hess, Christopher, Kibarian, John, Lee, Sherry, Liao, Marci, Lin, Sheng-Che, Matsuhashi, Hideki, Michaels, Kimon, O'Sullivan, Conor, Rauscher, Markus, Rovner, Vyacheslav, Strojwas, Andrzej, Strojwas, Marcin, Taylor, Carl, Vallishayee, Rakesh, Weiland, Larg, Yokoyama, Nobuharu
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US15/090,274
• Time in Patent Office: 575 Days
• Field of Search: 438 11- 18, 257 48
• CPC Class Codes: G01N 23/2251 using incident electron beams, e.g. scanning electron microscopy [SEM]
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, and may include NCEM pads that comprise a mesh of GATECNT and AACNT stripes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

Claims

1. On a semiconductor substrate a mesh-style non-contact electrical measurement (NCEM) pad that includes a mask-patterned gate (GATE), a source/drain (AA), a source/drain silicide (TS), a gate contact (GATECNT), and source/drain contact (AACNT) features, comprising:

at least two parallel, elongated AACNT features extending longitudinally in a first direction; and

at least two parallel, elongated GATECNT features extending longitudinally in a second direction perpendicular to the first direction, wherein said features are positioned such that each of said AANCT features intersects each of said GATECNT features.

2. A mesh-style NCEM pad, as defined in claim 1, wherein said pad includes at least three parallel, elongated AACNT features that extend longitudinally in the first direction.

3. A mesh-style NCEM pad, as defined in claim 1, wherein said pad includes at least four parallel, elongated AACNT features that extend longitudinally in the first direction.

4. A mesh-style NCEM pad, as defined in claim 1, wherein said pad includes at least five parallel, elongated AACNT features that extend longitudinally in the first direction.

5. A mesh-style NCEM pad, as defined in claim 1, wherein said pad includes at least three parallel, elongated GATECNT features that extend longitudinally in the second direction.

6. A mesh-style NCEM pad, as defined in claim 1, wherein said pad includes at least four parallel, elongated GATECNT features that extend longitudinally in the second direction.

7. A mesh-style NCEM pad, as defined in claim 1, wherein said pad includes at least five parallel, elongated GATECNT features that extend longitudinally in the second direction.

8. A mesh-style NCEM pad, as defined in claim 1, wherein said AACNT features are multi-patterned, with at least some of said elongated AACNT features patterned by a first color (AACNTm1) mask, and at least some of said elongated AACNT features patterned by a second color (AACNTm2) mask.

9. A mesh-style NCEM pad, as defined in claim 1, wherein said AACNT features are multi-patterned, with at least some of said elongated AACNT features patterned by a first color (AACNTm1) mask, at least some of said elongated AACNT features patterned by a second color (AACNTm2) mask, and at least some of said elongated AACNT features patterned by a third color (AACNTm3) mask.

10. A mesh-style NCEM pad, as defined in claim 1, wherein said GATECNT features are multi-patterned, with at least some of said elongated GATECNT features patterned by a first color (GATECNTm1) mask, and at least some of said elongated GATECNT features patterned by a second color (GATECNTm2) mask.

11. A mesh-style NCEM pad, as defined in claim 1, wherein said GATECNT features are multi-patterned, with at least some of said elongated GATECNT features patterned by a first color (GATECNTm1) mask, at least some of said elongated GATECNT features patterned by a second color (GATECNTm2) mask, and at least some of said elongated GATECNT features patterned by a third color (GATECNTm3) mask.

12. A mesh-style NCEM pad, as defined in claim 1, wherein said pad is contained within a fill cell selected from the list the consists of:

AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-tip-short-configured, NCEM-enabled fill cells;

AACNT-TS-tip-to-tip-short-configured, NCEM-enabled fill cells;

TS-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V0-tip-to-tip-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-tip-short-configured, NCEM-enabled fill cells;

first interconnect via layer (V1)-M1-tip-to-tip-short-configured, NCEM-enabled fill cells;

V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

second wiring layer (M2)-tip-to-tip-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-tip-short-configured, NCEM-enabled fill cells;

second interconnect via layer (V2)-M2-tip-to-tip-short-configured, NCEM-enabled fill cells;

third wiring layer (M3)-tip-to-tip-short-configured, NCEM-enabled fill cells;

V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-tip-short-configured, NCEM-enabled fill cells;

AA-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATE-AA-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

TS-GATECNT-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-tip-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-TS-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V0-tip-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-tip-to-side-short-configured, NCEM-enabled fill cells;

V1-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-tip-to-side-short-configured, NCEM-enabled fill cells;

V2-tip-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-tip-to-side-short-configured, NCEM-enabled fill cells;

AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-AA-side-to-side-short-configured, NCEM-enabled fill cells;

AACNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

TS-GATE-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-side-to-side-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-side-to-side-short-configured, NCEM-enabled fill cells;

M1-side-to-side-short-configured, NCEM-enabled fill cells;

V0-side-to-side-short-configured, NCEM-enabled fill cells;

M1-V0-side-to-side-short-configured, NCEM-enabled fill cells;

V1-M1-side-to-side-short-configured, NCEM-enabled fill cells;

V1-side-to-side-short-configured, NCEM-enabled fill cells;

M2-side-to-side-short-configured, NCEM-enabled fill cells;

M2-V1-side-to-side-short-configured, NCEM-enabled fill cells;

V2-M2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-side-to-side-short-configured, NCEM-enabled fill cells;

V2-side-to-side-short-configured, NCEM-enabled fill cells;

M3-V2-side-to-side-short-configured, NCEM-enabled fill cells;

AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AACNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATE-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AA-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-TS-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATE-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V0-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-AACNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-GATECNT-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V1-V0-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-M1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-V1-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

V2-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-M2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

M3-V2-L-shape-interlayer-short-configured, NCEM-enabled fill cells;

AA-diagonal-short-configured, NCEM-enabled fill cells;

TS-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-diagonal-short-configured, NCEM-enabled fill cells;

AACNT-AA-diagonal-short-configured, NCEM-enabled fill cells;

GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATE-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-diagonal-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-diagonal-short-configured, NCEM-enabled fill cells;

M1-diagonal-short-configured, NCEM-enabled fill cells;

V0-diagonal-short-configured, NCEM-enabled fill cells;

M1-V0-diagonal-short-configured, NCEM-enabled fill cells;

V1-M1-diagonal-short-configured, NCEM-enabled fill cells;

V1-diagonal-short-configured, NCEM-enabled fill cells;

M2-diagonal-short-configured, NCEM-enabled fill cells;

M2-V1-diagonal-short-configured, NCEM-enabled fill cells;

M3-diagonal-short-configured, NCEM-enabled fill cells;

V2-M2-diagonal-short-configured, NCEM-enabled fill cells;

V2-diagonal-short-configured, NCEM-enabled fill cells;

M3-V2-diagonal-short-configured, NCEM-enabled fill cells;

AA-corner-short-configured, NCEM-enabled fill cells;

AACNT-corner-short-configured, NCEM-enabled fill cells;

AACNT-AA-corner-short-configured, NCEM-enabled fill cells;

GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-GATE-corner-short-configured, NCEM-enabled fill cells;

GATECNT-TS-corner-short-configured, NCEM-enabled fill cells;

GATECNT-corner-short-configured, NCEM-enabled fill cells;

GATECNT-AA-corner-short-configured, NCEM-enabled fill cells;

GATECNT-AACNT-corner-short-configured, NCEM-enabled fill cells;

M1-corner-short-configured, NCEM-enabled fill cells;

V0-corner-short-configured, NCEM-enabled fill cells;

M1-V0-corner-short-configured, NCEM-enabled fill cells;

V1-M1-corner-short-configured, NCEM-enabled fill cells;

V1-corner-short-configured, NCEM-enabled fill cells;

M2-corner-short-configured, NCEM-enabled fill cells;

M2-V1-corner-short-configured, NCEM-enabled fill cells;

M3-corner-short-configured, NCEM-enabled fill cells;

V2-M2-corner-short-configured, NCEM-enabled fill cells;

V2-corner-short-configured, NCEM-enabled fill cells;

M3-V2-corner-short-configured, NCEM-enabled fill cells;

GATE-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATE-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

GATECNT-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AA-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-TS-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATE-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-GATECNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M1-AACNT-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V1-V0-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M2-M1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V2-V1-interlayer-overlap-short-configured, NCEM-enabled fill cells;

M3-M2-interlayer-overlap-short-configured, NCEM-enabled fill cells;

V0-GATECNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-AACNT-via-chamfer-short-configured, NCEM-enabled fill cells;

V1-M1-via-chamfer-short-configured, NCEM-enabled fill cells;

V2-M2-via-chamfer-short-configured, NCEM-enabled fill cells;

third interconnect via layer (V3)-M3-via-chamfer-short-configured, NCEM-enabled fill cells;

V0-merged-via-short-configured, NCEM-enabled fill cells;

V1-merged-via-short-configured, NCEM-enabled fill cells;

V2-merged-via-short-configured, NCEM-enabled fill cells;

AA-snake-open-configured, NCEM-enabled fill cells;

TS-snake-open-configured, NCEM-enabled fill cells;

AACNT-snake-open-configured, NCEM-enabled fill cells;

GATE-snake-open-configured, NCEM-enabled fill cells;

GATECNT-snake-open-configured, NCEM-enabled fill cells;

V0-snake-open-configured, NCEM-enabled fill cells;

M1-snake-open-configured, NCEM-enabled fill cells;

M1-V0-AACNT-snake-open-configured, NCEM-enabled fill cells;

V1-snake-open-configured, NCEM-enabled fill cells;

M2-snake-open-configured, NCEM-enabled fill cells;

V2-snake-open-configured, NCEM-enabled fill cells;

M3-snake-open-configured, NCEM-enabled fill cells;

AA-stitch-open-configured, NCEM-enabled fill cells;

TS-stitch-open-configured, NCEM-enabled fill cells;

AACNT-stitch-open-configured, NCEM-enabled fill cells;

GATECNT-stitch-open-configured, NCEM-enabled fill cells;

V0-stitch-open-configured, NCEM-enabled fill cells;

M1-stitch-open-configured, NCEM-enabled fill cells;

V1-stitch-open-configured, NCEM-enabled fill cells;

M2-stitch-open-configured, NCEM-enabled fill cells;

V2-stitch-open-configured, NCEM-enabled fill cells;

M3-stitch-open-configured, NCEM-enabled fill cells;

AACNT-TS-via-open-configured, NCEM-enabled fill cells;

AACNT-AA-via-open-configured, NCEM-enabled fill cells;

TS-AA-via-open-configured, NCEM-enabled fill cells;

GATECNT-GATE-via-open-configured, NCEM-enabled fill cells;

GATECNT-AACNT-via-open-configured, NCEM-enabled fill cells;

GATECNT-AACNT-GATE-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-via-open-configured, NCEM-enabled fill cells;

V0-AA-via-open-configured, NCEM-enabled fill cells;

V0-TS-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-via-open-configured, NCEM-enabled fill cells;

V0-GATE-via-open-configured, NCEM-enabled fill cells;

V0-via-open-configured, NCEM-enabled fill cells;

M1-V0-via-open-configured, NCEM-enabled fill cells;

V1-via-open-configured, NCEM-enabled fill cells;

V1-M1-via-open-configured, NCEM-enabled fill cells;

V1-M2-via-open-configured, NCEM-enabled fill cells;

M1-GATECNT-via-open-configured, NCEM-enabled fill cells;

M1-AANCT-via-open-configured, NCEM-enabled fill cells;

V2-M2-via-open-configured, NCEM-enabled fill cells;

V2-M3-via-open-configured, NCEM-enabled fill cells;

V3-via-open-configured, NCEM-enabled fill cells;

fourth wiring layer (M4)-V3-via-open-configured, NCEM-enabled fill cells;

fifth wiring layer (M5)-fourth interconnect via layer (V4)-via-open-configured, NCEM-enabled fill cells;

M1-metal-island-open-configured, NCEM-enabled fill cells;

M2-metal-island-open-configured, NCEM-enabled fill cells;

M3-metal-island-open-configured, NCEM-enabled fill cells;

V0-merged-via-open-configured, NCEM-enabled fill cells;

V0-AACNT-merged-via-open-configured, NCEM-enabled fill cells;

V0-GATECNT-merged-via-open-configured, NCEM-enabled fill cells;

V1-merged-via-open-configured, NCEM-enabled fill cells;

V2-merged-via-open-configured, NCEM-enabled fill cells;

V1-M1-merged-via-open-configured, NCEM-enabled fill cells; and

,

V2-M2-merged-via-open-configured, NCEM-enabled fill cells.

13. An NCEM pad assembly that includes:

a mesh-style NCEM pad as defined in claim 1; and

an upper layer NCEM pad overlying the mesh-style NCEM pad, said upper layer NCEM pad comprising;

one or more mask-patterned features, in a first wiring layer (M1), that substantially cover the mesh-style NCEM pad; and

one or more mask-patterned features, in a via to interconnect stack (VO) layer, that provide electrical connection(s) between the M1 feature(s) and the mesh-style NCEM pad.

14. An NCEM pad assembly, as defined in claim 13, wherein said V0 features are positioned at the intersections of the underlying AACNT and GATECNT features.

15. An NCEM pad assembly, as defined in claim 13, wherein said V0 features are positioned to avoid intersections of the underlying AACNT and GATECNT features.

16. An NCEM pad assembly, as defined in claim 13, wherein said one or more M1 features include multiple parallel, elongated M1 features.

17. An NCEM pad assembly, as defined in claim 16, wherein said elongated M1 features are multi-patterned, with at least some of said elongated M1 features patterned by a first color (M1m1) mask, and at least some of said elongated M1 features patterned by a second color (M1m2) mask.

18. An NCEM pad assembly, as defined in claim 16, wherein said elongated M1 features are multi-patterned, with at least some of said elongated M1 features patterned by a first color (M1m1) mask, at least some of said elongated M1 features patterned by a second color (M1m2) mask, and at least some of said elongated M1 features patterned by a third color (M1m3) mask.