Chip package having die structures of different heights and method of forming same

• US 9,806,058 B2
• Filed: 01/21/2016
• Issued: 10/31/2017
• Est. Priority Date: 07/02/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wei, Wen-Hsin, Wu, Chi-Hsi, Yu, Chen-Hua, Hu, Hsien-Pin, Hou, Shang-Yun, Chen, Wei-Ming
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US15/003,150
• Publication Number:
  US 20170005072A1
• Time in Patent Office: 649 Days
• Field of Search: 257773, 257774, 257686, 257685, 257723, 257728, 257777, 257784, 257786, 257787, 257788
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08235 the bonding area connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/09 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/182 : Disposition

Abstract

Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

Claims

1. A chip package, comprising:

a chip stack including a plurality of semiconductor dies;

a semiconductor chip, wherein the semiconductor chip is higher than the chip stack; and

a package layer overfilling a gap between the chip stack and the semiconductor chip, the package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

2. The chip package as claimed in claim 1, wherein a top surface of the semiconductor chip is not covered by the package layer.

3. The chip package as claimed in claim 1, further comprising a substrate, wherein the chip stack and the semiconductor chip are bonded on the substrate through conductive bonding structures.

4. The chip package as claimed in claim 3, wherein the substrate is a semiconductor substrate.

5. The chip package as claimed in claim 4, further comprising a conductive feature penetrating through the substrate and electrically connected to one of the conductive bonding structures.

6. The chip package as claimed in claim 3, wherein the package layer surrounds and is in direct contact with the conductive bonding structures.

7. The chip package as claimed in claim 3, further comprising an underfill layer surrounding and in direct contact with the conductive bonding structures, wherein the underfill layer is between the substrate and the package layer.

8. The chip package as claimed in claim 7, wherein the underfill layer is in direct contact with the package layer.

9. The chip package as claimed in claim 1, wherein the chip stack comprises a plurality of memory dies.

10. The chip package as claimed in claim 1, wherein a top surface of the package layer is substantially coplanar with a top surface of the semiconductor chip.

11. The chip package as claimed in claim 1, wherein the chip stack comprises a molding compound layer surrounding the plurality of semiconductor dies.

12. A chip package, comprising:

a first semiconductor chip;

a second semiconductor chip; and

a molding compound layer surrounding the first semiconductor chip and the second semiconductor chip, wherein the molding compound layer covers a top surface of the first semiconductor chip, and a top surface of the molding compound layer is substantially coplanar with a top surface of the second semiconductor chip.

13. The chip package as claimed in claim 12, wherein the second semiconductor chip is higher than the first semiconductor chip.

14. The chip package as claimed in claim 12, further comprising a substrate, wherein the first semiconductor chip and the second semiconductor chip are bonded on the substrate through conductive bonding structures.

15. The chip package as claimed in claim 14, further comprising a conductive feature penetrating through the substrate and electrically connected to one of the conductive bonding structures.

16. The chip package as claimed in claim 14, wherein the molding compound layer surrounds and is in direct contact with the conductive bonding structures.

17. A method for forming a chip package, comprising:

bonding a first semiconductor chip and a second semiconductor chip over a substrate;

forming a package layer over the substrate to encapsulate the first semiconductor chip and the second semiconductor chip; and

planarizing the package layer so that a top surface of the second semiconductor chip is exposed, and a top surface of the first semiconductor chip is covered by the package layer.

18. The method for forming a chip package as claimed in claim 17, wherein the first semiconductor chip is not ground during the planarization process.

19. The method for forming a chip package as claimed in claim 17, wherein the first semiconductor chip and the second semiconductor chip are bonded onto the substrate through a plurality of conductive bonding structures.

20. The method for forming a chip package as claimed in claim 19, further comprising forming an underfill layer to surround the conductive bonding structures before the formation of the package layer.