FinFET spacer formation on gate sidewalls, between the channel and source/drain regions

• US 9,806,078 B1
• Filed: 11/02/2016
• Issued: 10/31/2017
• Est. Priority Date: 11/02/2016
• Status: Expired due to Fees

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Xie, Ruilong, Prindle, Christopher, Yamashita, Tenko, Pranatharthiharan, Balasubramanian, Montanini, Pietro, Seo, Soon-Cheon
• Primary Examiner(s): Wilczewski, Mary
• Application Number:
  US15/341,240
• Time in Patent Office: 363 Days
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7856 with an non-uniform gate, e.g. varying doping structure, shape or composition on different sides of the fin, or different gate insulator thickness or composition on opposing fin sides H01L29/7855 takes precedence

Abstract

FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

Claims

1. A method comprising:

providing an intermediate semiconductor structure comprising a substrate having one or more fin having a first plurality and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first plurality and the second plurality of gates;

depositing a first liner on the intermediate semiconductor structure;

depositing a fill material at a level along inner portions of the first liner between the first plurality and second plurality of gates adjacent to the one or more fin;

removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner disposed adjacent to the one or more fin defining a first thickness; and

depositing a second liner having a second thickness over the first plurality and the second plurality of gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.

2. The method of claim 1 wherein the depositing the fill material comprises depositing the fill material over the first liner and above the first plurality and the second plurality of gates, and removing a portion of the fill material to the level along inner portions of the first liner.

3. The method of claim 2 wherein the removing the portion of the fill material comprises first removing a portion of the fill material stopping at the first liner above the first plurality and the second plurality of spaced apart gates.

4. The method of claim 3 wherein the first removing comprises a chemical mechanical polishing.

5. The method of claim 3 wherein the removing the portion of the fill material comprises a second removing of a portion of the fill material to the level along inner portions of the first liner.

6. The method of claim 1 further comprising:

depositing a first blocking material over the second liner disposed on the first plurality of gates; and

removing a portion of the second liner, the fill material, and the first liner disposed between the second plurality of gates to expose portions of the one or more fin between the second plurality of gates.

7. The method of claim 6 wherein the removing the portion of the second liner comprises anisotropically removing the second liner disposed between the second plurality of gates, and the removing the first liner comprises anisotropically removing the first liner disposed between the second plurality of gates.

8. The method of claim 7 further comprising removing the first blocking material.

9. The method of claim 8 further comprising:

forming source/drain regions on the one or more fin adjacent to the remaining first spacers and first liner between the second plurality of gates.

10. The method of claim 9 further comprising depositing a third liner over the first plurality and second plurality of gates.

11. The method of claim 10 further comprising

depositing a second blocking material over the third liner disposed on the second plurality of gates;

and

removing a portion of the third liner, the second liner, the fill material, and the first liner disposed between the first plurality of gates to expose portions of the one or more fin between the first plurality of gates.

12. The method of claim 11 further comprising:

removing the second blocking material; and

forming source/drain regions on the one or more fin adjacent to the remaining first spacers and first liner between the first plurality of gates.

13. The method of claim 12 further comprising:

removing the remaining third liner.

14. The method of claim 12 wherein the first plurality of gates and first source/drain regions are operable for forming nFETS, and the second plurality of gates and second source/drain regions are operable for forming pFETS.

15. The method of claim 12 wherein the remaining first spacers and first liner between the first plurality of gates and between the second plurality of gates have equal thicknesses.

16. The method of claim 13 further comprising:

depositing a fourth liner on and between the first plurality of gates, and on and between the second plurality of gates.

17. The method of claim 1 wherein the first and second plurality of gates comprise dummy gates.