Semiconductor device

• US 9,806,079 B2
• Filed: 11/24/2015
• Issued: 10/31/2017
• Est. Priority Date: 10/29/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Imai, Keitaro, Koyama, Jun
• Primary Examiner(s): Sengdara, Vongsavanh
• Application Number:
  US14/950,624
• Publication Number:
  US 20160079245A1
• Time in Patent Office: 707 Days
• Field of Search: 257 43
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10⁻¹³ A or less.

Claims

1. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising a first semiconductor layer including a first channel formation region, a first gate electrode, a first source electrode and a first drain electrode;

a logic circuit comprising a second transistor over the substrate, the second transistor comprising a second semiconductor layer including a second channel formation region, a second gate electrode, a second source electrode and a second drain electrode; and

a capacitor over the substrate, the capacitor comprising two electrodes,

wherein the first transistor is provided over the logic circuit,

wherein one of the first source electrode and the first drain electrode is electrically connected to the second gate electrode of the second transistor, and one of the electrodes of the capacitor,

wherein the first transistor is electrically separated from the other of the electrodes of the capacitor, and

wherein the first semiconductor layer comprises an oxide semiconductor in the first channel formation region.

2. The semiconductor device according to claim 1, wherein an off-current of the first transistor is 1×

10<sup>−

17</sup> A/μ

m or less.

3. The semiconductor device according to claim 1,

wherein the logic circuit comprises an inverter, and

wherein the second transistor is included in the inverter.

4. The semiconductor device according to claim 1, wherein the semiconductor device is designed so that an input signal is applied to the logic circuit through the first transistor when the first transistor is in an on state, and the input signal is stored at the second gate electrode of the second transistor when the first transistor is in an off state.

5. The semiconductor device according to claim 1, wherein the first transistor is provided above the logic circuit.

6. A semiconductor device comprising:

a first transistor over a substrate, the first transistor comprising a first semiconductor layer including a first channel formation region, a first gate electrode, a first source electrode and a first drain electrode;

an insulating layer over the first transistor, the insulating layer including an opening;

a first electrode in the opening, the first electrode being in contact with one of the first source electrode and the first drain electrode;

a logic circuit comprising a second transistor over the substrate, the second transistor comprising a second semiconductor layer including a second channel formation region, a second gate electrode, a second source electrode and a second drain electrode;

a second electrode in contact with the second gate electrode; and

a capacitor over the substrate, the capacitor comprising two electrodes,

wherein the first transistor is provided over the logic circuit,

wherein the one of the first source electrode and the first drain electrode is electrically connected to the second gate electrode of the second transistor through the first electrode and the second electrode, and is electrically connected to one of the electrodes of the capacitor,

wherein the first transistor is electrically separated from the other of the electrodes of the capacitor,

wherein the first semiconductor layer comprises an oxide semiconductor in the first channel formation region, and

wherein a top surface of the first electrode is effectively in conformity to a top surface of the insulating layer.

7. The semiconductor device according to claim 6, wherein the first electrode and the insulating layer are planarized by CMP method.

8. The semiconductor device according to claim 6, wherein an off-current of the first transistor is 1×

10<sup>−

17</sup> A/μ

m or less.

9. The semiconductor device according to claim 6,

wherein the logic circuit comprises an inverter, and

wherein the second transistor is included in the inverter.

10. The semiconductor device according to claim 6, wherein the semiconductor device is designed so that an input signal is applied to the logic circuit through the first transistor when the first transistor is in an on state, and the input signal is stored at the second gate electrode of the second transistor when the first transistor is in an off state.

11. The semiconductor device according to claim 6, wherein the first transistor is provided above the logic circuit.

12. The semiconductor device according to claim 6, wherein the first electrode and the second electrode do not overlap each other.