Semiconductor memory device and methods for manufacturing the same

• US 9,806,092 B1
• Filed: 03/17/2017
• Issued: 10/31/2017
• Est. Priority Date: 09/12/2016
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Minemura, Yoichi
• Primary Examiner(s): Fourson, III, George
• Application Number:
  US15/461,590
• Time in Patent Office: 228 Days
• Field of Search: 257330, 438270
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a semiconductor memory device includes first to fourth conductive layers, a first intermediate insulating layer, a second intermediate insulating layer, an inter-layer insulating layer, a first semiconductor body, a first memory layer, a second semiconductor body, a second memory layer, and a first interconnect. The second conductive layer is separated from the first conductive layer in a first direction. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is separated from the third conductive layer in the first direction and arranged with the second conductive layer in the second direction. The first intermediate insulating layer is provided between the first conductive layer and the third conductive layer. The second intermediate insulating layer is provided between the second conductive layer and the fourth conductive layer.

Claims

1. A semiconductor memory device, comprising:

a first conductive layer;

a second conductive layer separated from the first conductive layer in a first direction;

a third conductive layer arranged with the first conductive layer in a second direction crossing the first direction;

a fourth conductive layer separated from the third conductive layer in the first direction and arranged with the second conductive layer in the second direction;

a first intermediate insulating layer provided between the first conductive layer and the third conductive layer;

a second intermediate insulating layer provided between the second conductive layer and the fourth conductive layer;

an inter-layer insulating layer including an intermediate partial region, the intermediate partial region being between the first intermediate insulating layer and the second intermediate insulating layer;

a first semiconductor body extending through the first conductive layer and the second conductive layer in the first direction;

a first memory layer provided between the first conductive layer and the first semiconductor body;

a second semiconductor body extending through the third conductive layer and the fourth conductive layer in the first direction;

a second memory layer provided between the third conductive layer and the second semiconductor body; and

a first interconnect electrically connected to the first semiconductor body and the second semiconductor body,

at least one of the first intermediate insulating layer or the second intermediate insulating layer including a material different from a material of the intermediate partial region.

2. The semiconductor memory device according to claim 1, wherein

the first intermediate insulating layer and the second intermediate insulating layer include silicon nitride, and

the intermediate partial region includes silicon oxide.

3. The semiconductor memory device according to claim 2, wherein

the inter-layer insulating layer further includes a first partial region and a second partial region, the first partial region being between the first conductive layer and the second conductive layer, the second partial region being between the third conductive layer and the fourth conductive layer, and

the first partial region and the second partial region include silicon oxide.

4. The semiconductor memory device according to claim 3, wherein the intermediate partial region is continuous with the first partial region and continuous with the second partial region.

5. The semiconductor memory device according to claim 1, wherein a concentration of nitrogen of at least one of the first intermediate insulating layer or the second intermediate insulating layer is higher than a concentration of nitrogen in the intermediate partial region.

6. The semiconductor memory device according to claim 1, wherein a concentration of oxygen in the intermediate partial region is higher than a concentration of oxygen of at least one of the first intermediate insulating layer or the second intermediate insulating layer.

7. The semiconductor memory device according to claim 1, further comprising a barrier metal film provided between the first conductive layer and the first memory layer,

at least a portion of a region between the first intermediate insulating layer and the first conductive layer including a same material as the barrier metal film.

8. The semiconductor memory device according to claim 1, further comprising a first intermediate film provided between the first conductive layer and the first memory layer,

a dielectric constant of the first intermediate film being higher than a dielectric constant of the first intermediate insulating layer, and

at least a portion of a region between the first intermediate insulating layer and the first conductive layer including same material as the first intermediate film.

9. The semiconductor memory device according to claim 1, further comprising:

an intermediate semiconductor body extending through the first intermediate insulating layer, the second intermediate insulating layer, and the intermediate partial region in the first direction; and

an insulating portion provided between the intermediate semiconductor body and the first interconnect in the first direction.

10. The semiconductor memory device according to claim 9, wherein the intermediate semiconductor body is electrically insulated from at least one of the first interconnect or the base semiconductor layer.

11. The semiconductor memory device according to claim 9, further comprising a memory material film provided between the first intermediate insulating layer and the intermediate semiconductor body, the memory material film including a material included in the first memory layer.

12. The semiconductor memory device according to claim 1, wherein a distance between the first intermediate insulating layer and the first semiconductor body is 200 micrometers or less.

13. The semiconductor memory device according to claim 1, wherein a distance between the first intermediate insulating layer and the first semiconductor body is 100 micrometers or less.

14. The semiconductor memory device according to claim 1, wherein a distance between the first intermediate insulating layer and the first semiconductor body is 50 micrometers or less.

15. The semiconductor memory device according to claim 1, wherein

the first memory layer includes:

a memory film;

a first memory insulating film provided between the memory film and the first conductive layer; and

a second memory insulating film provided between the memory film and the first semiconductor body.

16. A method for manufacturing a semiconductor memory device, comprising:

forming a stacked film by alternately stacking a first film and a second film on a base semiconductor layer, the stacked film including a plurality of the first films and a plurality of the second films;

forming a first pillar-shaped structure body and a second pillar-shaped structure body, the first pillar-shaped structure body including a first semiconductor body and a first memory layer, the first semiconductor body extending through the stacked film along a stacking direction of the stacked film, the first memory layer being provided between the first semiconductor body and the stacked film, the second pillar-shaped structure body including a second semiconductor body and a second memory layer, the second semiconductor body extending through the stacked film along the stacking direction, the second memory layer being provided between the second semiconductor body and the stacked film;

forming a hole in the stacked film;

causing a third portion of the plurality of first films to remain while removing a first portion and a second portion of the plurality of first films via the hole, the third portion being positioned between the first pillar-shaped structure body and the second pillar-shaped structure body, the first portion being positioned between the third portion and the first pillar-shaped structure body, the second portion being positioned between the third portion and the second pillar-shaped structure body;

forming a plurality of conductive layers from a conductive material by introducing the conductive material to at least a portion of a space formed by the removing of the first portion and the second portion; and

forming an interconnect electrically connected to the first semiconductor body and the second semiconductor body.

17. The method for manufacturing the semiconductor memory device according to claim 16, wherein

the first film includes silicon nitride, and

the second film includes silicon oxide.

18. The method for manufacturing the semiconductor memory device according to claim 16, further comprising forming a third film inside the space on at least a portion of the plurality of second films, the first pillar-shaped structure body, and the second pillar-shaped structure body, the forming of the third film being performed between the removing of the first portion and the second portion and the introducing of the conductive material, the third film including TiN.

19. The method for manufacturing the semiconductor memory device according to claim 18, further comprising forming a fourth film inside the space between the forming of the third film and the introducing of the conductive material, the fourth film including an oxide including at least one selected from the group consisting of aluminum and hafnium.

20. The method for manufacturing the semiconductor memory device according to claim 18, further comprising forming a fourth film inside the space between the forming of the third film and the introducing of the conductive material, the fourth film including an oxide,

a dielectric constant of the fourth film being higher than a dielectric constant of the second film.