Method for manufacturing a semiconductor device

• US 9,806,187 B2
• Filed: 10/16/2012
• Issued: 10/31/2017
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin
• Primary Examiner(s): Enad, Christine
• Application Number:
  US13/652,758
• Publication Number:
  US 20130040443A1
• Time in Patent Office: 1,841 Days
• Field of Search: 438478, 438589, 257E2109
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor body having a horizontal surface;

forming an epitaxy hard mask on the horizontal surface;

depositing a semiconductor material on the semiconductor body by epitaxial deposition selective to the epitaxy hard mask by selective epitaxy so that, in a vertical cross-section, at least two spaced apart epitaxial regions are formed;

removing the epitaxy hard mask selective to the semiconductor material so that, in the vertical cross-section, sidewalls of the at least two spaced apart epitaxial regions are exposed;

forming a trench hard mask comprising forming a dielectric layer so that, in the vertical cross-section, each of the sidewalls of the at least two spaced apart epitaxial regions is covered by the dielectric layer;

etching a vertical trench into the semiconductor body using the trench hard mask as an etching mask; and

forming an insulated gate electrode which is, in the vertical cross-section, arranged between the at least two spaced apart epitaxial regions.

2. The method of claim 1, further comprising polishing the semiconductor material back to the epitaxy hard mask.

3. The method of claim 1, wherein forming the epitaxy hard mask comprises at least one of:

forming a thermal oxide layer; and

depositing a nitride layer and depositing a TEOS layer.

4. The method of claim 1, further comprising forming an insulated field plate in a lower portion of the vertical trench.

5. The method of claim 1, wherein the semiconductor device comprises an active area and a peripheral area, the method further comprising:

forming a plurality of vertical trenches in the active area and at least one vertical trench in the peripheral area; and

forming insulated gate electrodes only in the active area.

6. The method of claim 1, wherein the epitaxy hard mask has a vertical extension of about 300 nm to about 600 nm.

7. The method of claim 1, wherein the epitaxy hard mask comprises at least one of a thermal oxide layer, a TEOS layer, an undoped silicate glass layer, a high density plasma oxide layer, and a doped oxide layer.