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Method for fabricating transistor with thinned channel

  • US 9,806,195 B2
  • Filed: 03/14/2016
  • Issued: 10/31/2017
  • Est. Priority Date: 06/15/2005
  • Status: Active Grant
First Claim
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1. A mobile computing device, comprising:

  • one or more electronic memories; and

    one or more processors coupled to the memories by a bus, wherein at least one of the processors includes at least one transistor further comprising;

    a semiconductor body disposed over a substrate, the semiconductor body having a first width, a second width, a length, and a height;

    a source region disposed within a first end of the semiconductor body having the first width and the height;

    a drain region disposed within a second end of the semiconductor body having the first width and the height, the second end opposite the first end;

    a channel region disposed only in a portion of the semiconductor body having the second width and the height and disposed between the source region and the drain region, wherein;

    the length of the semiconductor body runs from the source region through the channel region to the drain region;

    the second width is narrower than the first width;

    the height of the semiconductor body is taken from an interface of the substrate and the semiconductor body to a top surface of the semiconductor body opposite the substrate; and

    the first and second width are orthogonal to the length and the height;

    a gate stack disposed over the channel region, the gate stack having a distance between sidewalls of the gate stack equal to and in direct alignment with the length of the portion of the semiconductor body having the second width, wherein the gate stack comprises a gate dielectric layer and a gate electrode; and

    a pair of spacers adjacent to the sidewalls of the gate stack, wherein the pair of spacers are recessed into the semiconductor body.

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