Method for fabricating transistor with thinned channel

• US 9,806,195 B2
• Filed: 03/14/2016
• Issued: 10/31/2017
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Brask, Justin K., Chau, Robert S., Datta, Suman, Doczy, Mark L., Doyle, Brian S., Kavalieros, Jack T., Majumdar, Amlan, Metz, Matthew V., Radosavljevic, Marko
• Primary Examiner(s): Everhart, Caridad
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US15/069,726
• Publication Number:
  US 20160197185A1
• Time in Patent Office: 596 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H04B 1/3827 Portable transceivers
• CPC Class Codes: Y10S 438/926 : Dummy metallization

Abstract

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Claims

1. A mobile computing device, comprising:

one or more electronic memories; and

one or more processors coupled to the memories by a bus, wherein at least one of the processors includes at least one transistor further comprising;

a semiconductor body disposed over a substrate, the semiconductor body having a first width, a second width, a length, and a height;

a source region disposed within a first end of the semiconductor body having the first width and the height;

a drain region disposed within a second end of the semiconductor body having the first width and the height, the second end opposite the first end;

a channel region disposed only in a portion of the semiconductor body having the second width and the height and disposed between the source region and the drain region, wherein;

the length of the semiconductor body runs from the source region through the channel region to the drain region;

the second width is narrower than the first width;

the height of the semiconductor body is taken from an interface of the substrate and the semiconductor body to a top surface of the semiconductor body opposite the substrate; and

the first and second width are orthogonal to the length and the height;

a gate stack disposed over the channel region, the gate stack having a distance between sidewalls of the gate stack equal to and in direct alignment with the length of the portion of the semiconductor body having the second width, wherein the gate stack comprises a gate dielectric layer and a gate electrode; and

a pair of spacers adjacent to the sidewalls of the gate stack, wherein the pair of spacers are recessed into the semiconductor body.

2. The device of claim 1, wherein the one or more processors includes at least one of:

a central processing unit (CPU);

a graphics processor;

a digital signal processor;

or

a crypto processor.

3. The device of claim 1, further comprising a network interface coupled to at least one of processors by the bus.

4. The device of claim 1, wherein the one or more memories further comprise at least one of volatile and non-volatile memory.

5. The device of claim 1, wherein the channel region is directly adjacent to both the source region and the drain region.

6. The device of claim 5, further comprising:

a first tip region disposed within the first end of the semiconductor body having the first width; and

a second tip region disposed within the second end of the semiconductor body having the first width.

7. The device of claim 1, wherein the gate dielectric layer is disposed beneath the gate electrode and also forms the sidewalls of the gate stack.

8. The device of claim 1, wherein the gate dielectric layer is disposed only beneath the gate electrode.

9. The device of claim 1, wherein the gate dielectric layer comprises a high-k material layer, and the gate electrode comprises a metal layer disposed directly on the high-k material layer.

10. The device of claim 9, wherein the metal layer has a work function between 3.9 eV and 5.2 eV.

11. The device of claim 1, wherein the semiconductor body is disposed directly on a silicon-on-insulator substrate.

12. The device of claim 1, wherein the semiconductor body is disposed directly on a delta-doped substrate.

13. The mobile computing device of claim 1, wherein the pair of spacers include a carbon-doped nitride material.

14. The mobile computing device of claim 13, wherein the carbon-doped nitride material has carbon concentration in a range of 5% to 15%.

15. The mobile computing device of claim 1, wherein the pair of spacers includes N.

16. The mobile computing device of claim 1, wherein the source and drain regions comprise As or Ph.

17. The mobile computing device of claim 1, wherein the gate dielectric is a dual layer gate dielectric having a first layer and a second layer, wherein the first layer comprises Si and O, and wherein the second layer comprises Hf and O.

18. A mobile computing device, comprising:

one or more electronic memories; and

one or more processors coupled to the memories by a bus, wherein at least one of the processors includes at least one transistor further comprising;

a semiconductor body disposed above a substrate, the semiconductor body having a width, a length, a first height, and a second height;

a source region disposed within a first end of the semiconductor body having the first height and the width;

a drain region disposed within a second end of the semiconductor body, opposite the first, and having the first height and the width;

a channel region disposed within a portion of the semiconductor body having the second height and the width between the source region and the drain region,

wherein;

the second height is shorter than the first height;

the length of the semiconductor body runs from the source region through the channel region to the drain region;

the first and second heights of the semiconductor body are from an interface of the semiconductor body and the substrate to a top surface of the semiconductor body; and

the width is orthogonal to the length and the first and second heights; and

a gate stack disposed above the channel region, the gate stack having a distance between sidewalls of the gate stack equal to, and in direct alignment with, the length of the portion of the semiconductor body having the second height, wherein the gate stack comprises a gate dielectric layer and a gate electrode.

19. The device of claim 18, wherein the one or more processors includes at least one of:

a central processing unit (CPU);

a graphics processor;

a digital signal processor;

or

a crypto processor.

20. The device of claim 18, further comprising a network interface coupled to at least one of processors by the bus.

21. The device of claim 18, wherein the one or more memories further comprise at least one of volatile and non-volatile memory.

22. The device of claim 18, wherein the channel region is directly adjacent to both the source region and the drain region.

23. The device of claim 18, further comprising:

a first tip region disposed only in the first end of the semiconductor body having the width and the first height; and

a second tip region disposed only in the second end of the semiconductor body having the width and the first height, wherein the channel region is directly adjacent to both the first and second tip regions.

24. The device of claim 18, wherein the gate dielectric layer is disposed beneath the gate electrode and also forms the sidewalls of the gate stack.