Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator
First Claim
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1. A circuit, comprising:
- an injection-locked oscillator (ILO) having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output;
a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input;
a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output;
a phase detector (PD) having a first PD input, a second PD input, and a PD output;
a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and
wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input.
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Abstract
Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.
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Citations
20 Claims
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1. A circuit, comprising:
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an injection-locked oscillator (ILO) having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output; a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input; a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output; a phase detector (PD) having a first PD input, a second PD input, and a PD output; a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A controller device that controls the operation of a memory device, the controller device comprising:
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an injection-locked oscillator (ILO) having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output; a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input; a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output; a phase detector (PD) having a first PD input, a second PD input, and a PD output; a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A memory system, comprising:
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a memory module; and a memory controller coupled with the memory module via one or more signal lines, wherein the memory controller comprises an injection-locked-oscillator (ILO)-based clock deskew circuit, and wherein the ILO-based clock deskew circuit comprises; an ILO having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output; a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input; a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output; a phase detector (PD) having a first PD input, a second PD input, and a PD output; a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification