Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator

• US 9,806,727 B2
• Filed: 12/23/2016
• Issued: 10/31/2017
• Est. Priority Date: 03/03/2011
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Aleksi, Marko, Leibowitz, Brian S.
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US15/390,350
• Publication Number:
  US 20170207790A1
• Time in Patent Office: 312 Days
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Claims

1. A circuit, comprising:

an injection-locked oscillator (ILO) having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output;

a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input;

a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output;

a phase detector (PD) having a first PD input, a second PD input, and a PD output;

a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and

wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input.

2. The circuit of claim 1, wherein the ILO is based on a ring oscillator.

3. The circuit of claim 1, wherein the ILO is based on a tank circuit.

4. The circuit of claim 1, wherein the calibration circuit comprises frequency sweep circuitry to output a frequency control signal on the frequency control output that causes a free-running frequency of the ILO to sweep across a range of frequency values.

5. The circuit of claim 4, wherein the calibration circuit comprises storage circuitry to store a frequency control setting corresponding to the frequency control signal upon detecting that the calibration input indicates that phases of the first PD input and the second PD input are equal.

6. The circuit of claim 1, wherein the PSAD circuit adds a +45°

or −

45°

phase shift and a delay to an input PSAD signal received on the PSAD input.

7. The circuit of claim 6, wherein the PSAD circuit comprises a second ILO that is a replica of the ILO and a second multiplexer that is a replica of the multiplexer.

8. A controller device that controls the operation of a memory device, the controller device comprising:

an injection-locked oscillator (ILO) having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output;

a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input;

a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output;

a phase detector (PD) having a first PD input, a second PD input, and a PD output;

a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and

wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input.

9. The controller device of claim 8, wherein the ILO is based on a ring oscillator.

10. The controller device of claim 8, wherein the ILO is based on a tank circuit.

11. The controller device of claim 8, wherein the calibration circuit comprises frequency sweep circuitry to output a frequency control signal on the frequency control output that causes a free-running frequency of the ILO to sweep across a range of frequency values.

12. The controller device of claim 11, wherein the calibration circuit comprises storage circuitry to store a frequency control setting corresponding to the frequency control signal upon detecting that the calibration input indicates that phases of the first PD input and the second PD input are equal.

13. The controller device of claim 8, wherein the PSAD circuit adds a +45°

or −

45°

phase shift and a delay to an input PSAD signal received on the PSAD input.

14. The controller device of claim 13, wherein the PSAD circuit comprises a second ILO that is a replica of the ILO and a second multiplexer that is a replica of the multiplexer.

15. A memory system, comprising:

a memory module; and

a memory controller coupled with the memory module via one or more signal lines, wherein the memory controller comprises an injection-locked-oscillator (ILO)-based clock deskew circuit, and wherein the ILO-based clock deskew circuit comprises;

an ILO having an ILO free-running frequency control input, multiple ILO injection points, and an ILO output;

a multiplexer having a multiplexer input, multiple multiplexer outputs, and a multiplexer select input;

a phase-shift-and-delay (PSAD) circuit having a PSAD input and a PSAD output;

a phase detector (PD) having a first PD input, a second PD input, and a PD output;

a calibration circuit having a calibration input, an injection point select output, and a frequency control output; and

wherein an input clock signal is provided to the multiplexer input and the PSAD input, wherein each multiplexer output is coupled with a respective ILO injection point, wherein the ILO output is coupled with the first PD input, wherein the PSAD output is coupled with the second PD input, wherein the PD output is coupled with the calibration input, wherein the injection point select output is coupled with the multiplexer select input, and wherein the frequency control output is coupled with the ILO free-running frequency control input.

16. The memory system of claim 15, wherein the ILO is based on a ring oscillator.

17. The memory system of claim 15, wherein the ILO is based on a tank circuit.

18. The memory system of claim 15, wherein the calibration circuit comprises frequency sweep circuitry to output a frequency control signal on the frequency control output that causes a free-running frequency of the ILO to sweep across a range of frequency values.

19. The memory system of claim 18, wherein the calibration circuit comprises storage circuitry to store a frequency control setting corresponding to the frequency control signal upon detecting that the calibration input indicates that phases of the first PD input and the second PD input are equal.

20. The memory system of claim 15, wherein the PSAD circuit adds a +45°

or −

45°

phase shift and a delay to an input PSAD signal received on the PSAD input, and wherein the PSAD circuit comprises a second ILO that is a replica of the ILO and a second multiplexer that is a replica of the multiplexer.