Circuit for and method of receiving an input signal

• US 9,806,915 B1
• Filed: 06/27/2016
• Issued: 10/31/2017
• Est. Priority Date: 06/27/2016
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Elzeftawi, Mohamed N., Zhang, Hongtao
• Primary Examiner(s): Varndell, Ross
• Application Number:
  US15/194,302
• Time in Patent Office: 491 Days
• CPC Class Codes: H03B 2200/005 including measures to switch a capacitor
• CPC Class Codes: H03B 2200/0062 Bias and operating point
• CPC Class Codes: H03B 5/06 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03B 5/366 and comprising means for varying the frequency by a variable voltage or current
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 1/10 Means associated with receiver for limiting or suppressing noise or interference
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

A continuous time linear equalizer comprises an input of a first equalizer path configured to receive a first differential input signal; an input of a second equalizer path configured to receive a second differential input signal; a first programmable load capacitor coupled to an output of the first equalizer path; a second programmable load capacitor coupled to an output of the second equalizer path; and a programmable source capacitor coupled between the first equalizer path and the second equalizer path.

Claims

1. A continuous time linear equalizer comprising:

an input of a first equalizer path configured to receive a first signal of a differential input signal;

an input of a second equalizer path configured to receive a second signal of a differential input signal;

a first programmable load capacitor coupled to an output of the first equalizer path;

a second programmable load capacitor coupled to an output of the second equalizer path; and

a programmable source capacitor coupled between the first equalizer path and the second equalizer path.

2. The continuous time linear equalizer of claim 1 further comprising a first programmable load resistor coupled between the first equalizer path output and a voltage reference potential and a second programmable load resistor coupled between the second equalizer path output and the voltage reference potential.

3. The continuous time linear equalizer of claim 2 further comprising a first inductor coupled between the first programmable load resistor and the first equalizer path output and a second inductor coupled between the second programmable load resistor and the second equalizer path output.

4. The continuous time linear equalizer of claim 1 further comprising a source resistor coupled in parallel with the source capacitor between the first equalizer path and the second equalizer path.

5. The continuous time linear equalizer of claim 1 wherein the first equalizer path comprises a first transistor configured to receive the first signal of the differential input signal at a gate of the first transistor, and the second equalizer path comprises a second transistor configured to receive the second signal of the differential input signal at a gate of the second transistor.

6. The continuous time linear equalizer of claim 5 further comprising a first programmable current source coupled between the first transistor and a ground potential and a second programmable current source coupled between the second transistor and the ground potential.

7. The continuous time linear equalizer of claim 1 wherein a peaking frequency of an output signal of the continuous time linear equalizer is set by the first programmable load capacitor, the second programmable load capacitor and the programmable source capacitor.

8. The continuous time linear equalizer of claim 7 further comprising an automatic gain control circuit configured to control a gain of the input signal, and an automatic gain control adaptation circuit configured to control an adaptation of the automatic gain control circuit.

9. The continuous time linear equalizer of claim 8 further comprising a continuous time linear equalizer adaptation circuit configured to control an adaptation of the continuous time linear equalizer.

10. The continuous time linear equalizer of claim 1 wherein the input signal comprises a PAM4 signal.

11. A method of receiving an input signal, the method comprising:

receiving a differential input signal;

configuring a continuous time linear equalizer to receive a first signal of the differential input signal at a first equalizer input of a first equalizer path and a second signal of the differential input signal at a second equalizer input of a second equalizer path;

programming a first programmable load capacitor coupled to a first equalizer path output of the continuous time linear equalizer and a second programmable load capacitor coupled to a second equalizer path output of the continuous time linear equalizer; and

programming a programmable source capacitor coupled between the first equalizer path and the second equalizer path;

providing a high frequency gain boost with a fixed DC gain; and

coupling an output signal to first and second outputs of the continuous time linear equalizer.

12. The method of claim 11 further comprising setting a resistance of a first programmable load resistor coupled between the first equalizer path output and a voltage reference potential, and setting a resistance of a second programmable load resistor coupled between the second equalizer path output and the voltage reference potential.

13. The method of claim 12 further comprising coupling a first inductor between the first programmable load resistor and the first equalizer path output and coupling a second inductor between the second programmable load resistor and the second equalizer path output.

14. The method of claim 11 further comprising setting a resistance of a source resistor coupled in parallel with the source capacitor between the first equalizer path and the second equalizer path.

15. The method of claim 11 further comprising receiving the first signal of the differential input signal at a gate of a first transistor and receiving the second signal of the differential input signal at a gate of a second transistor.

16. The method of claim 15 further comprising coupling a first programmable current source between the first transistor and a ground potential, and coupling a second programmable current source between the second transistor and a ground potential.

17. The method of claim 11 further comprising setting a peaking frequency of the output signal of the continuous time linear equalizer using the first programmable load capacitor, the second programmable load capacitor and the programmable source capacitor.

18. The method of claim 17 further comprising configuring an automatic gain control circuit to control a gain of the input signal, and configuring an automatic gain control adaptation circuit to control an adaptation of the automatic gain control circuit.

19. The method of claim 18 further comprising configuring a continuous time linear equalizer adaptation circuit to control an adaptation of the continuous time linear equalizer.

20. The method of claim 11 wherein receiving a differential input signal comprises receiving a PAM4 signal.