Semiconductor device having a temperature circuit that provides a plurality of temperature operating ranges

• US 9,810,585 B2
• Filed: 04/30/2014
• Issued: 11/07/2017
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Jagan, Mirellys
• Application Number:
  US14/265,682
• Publication Number:
  US 20150276510A1
• Time in Patent Office: 1,287 Days
• Field of Search: 374170, 374163, 374100
• CPC Class Codes: G01K 13/00 Thermometers specially adapted for specific purposes
• CPC Class Codes: G01K 3/005 Circuits arrangements for indicating a predetermined temperature fire detection G08B17/00
• CPC Class Codes: G01K 7/00 Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat giving results other than momentary value of temperature G01K3/00 ; Power supply therefor, e.g. using thermoelectric elements
• CPC Class Codes: G01K 7/01 using semiconducting elements having PN junctions G01K7/02, G01K7/16, G01K7/30 take precedence
• CPC Class Codes: G01K 7/16 using resistive elements resistive elements per se H01C, H01L
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 21/10 comprising logic circuits
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A semiconductor device that may include at least one temperature sensing circuit is disclosed. The temperature sensing circuits may be used to control various operating parameters to improve the operation of the semiconductor device over a wide temperature range. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at other operating temperatures. The temperature sensing circuit may provide a plurality of temperature ranges for setting the operational parameters. Each temperature range can include a temperature range upper limit value and a temperature range lower limit value and adjacent temperature ranges may overlap. The temperature ranges may be set in accordance with a count value that can incrementally change in response to the at least one temperature sensing circuit.

Claims

1. A device, comprising:

a temperature circuit providing a plurality of temperature ranges, each temperature range having a temperature range upper limit value and a temperature range lower limit value, wherein adjacent ones of the plurality of temperature ranges overlap;

wherein

the temperature range lower limit value of an upper adjacent one of the temperature ranges is a lower temperature value than the temperature range upper limit value of a lower adjacent one of the temperature ranges.

2. The device of claim 1, wherein:

the device is a dynamic random access memory.

3. The device of claim 1, wherein:

the device is a semiconductor device.

4. The device of claim 1, wherein:

the temperature circuit includes

a first temperature sensor circuit that sets the temperature range upper limit value; and

a second temperature sensor circuit that sets the temperature range lower limit value.

5. The device of claim 4, further including:

a counter coupled to provide a count value having a range of unique values;

the first temperature sensor circuit coupled to receive the count value and sets one of the temperature range upper limit values for one of the plurality of temperature ranges for each unique value of the count value; and

the second temperature sensor circuit coupled to receive the count value and sets one of the temperature range lower limit values for one of the plurality of temperature ranges for each unique value of the count value.

6. The device of claim 1, further including:

a counter coupled to provide a count value having a range of unique values; and

the temperature circuit coupled to receive the count value and set one of the plurality of temperature ranges for each unique value of the count value.

7. The device of claim 6, wherein:

the counter incrementally changes the count value in a first direction in response to the temperature circuit detecting the temperature range upper limit value; and

the counter incrementally changes the count value in a second direction in response to the temperature circuit detecting the temperature range lower limit value.

8. The device of claim 7, further including:

a transition detector coupled to receive a least significant bit of the count value and provide a count transition pulse; and

the temperature circuit is coupled to receive the count transition pulse, the temperature circuit is disabled in response to the count transition pulse.

9. The device of claim 7, further including:

a count limit detector coupled to receive the count value and provide a first count limit detect signal; and

the temperature circuit is coupled to receive the first count limit detect signal, the temperature circuit includes a first output portion and the first output portion is disabled in response to the first count limit detect signal.

10. The device of claim 9, wherein:

the count limit detector provides a second count limit detect signal; and

the temperature circuit is coupled to receive the second count limit detect signal, the temperature circuit includes a second output portion and the second output portion is disabled in response to the second count limit detect signal.

11. The device of claim 6, further including:

a performance parameter table coupled to receive the count value and provide performance parameters in accordance with the count value.

12. The device of claim 11, further including:

a control circuit coupled to provide a read signal; and

the performance parameter table coupled to receive the read signal, the performance parameter table provides the performance parameters in response to the read signal.

13. The device of claim 11, wherein the performance parameter table includes a plurality of non-volatile memory cells.

14. The device of claim 11, further including:

latch circuits coupled to receive the performance parameters and provide latched performance parameters.

15. The device of claim 14, further including:

a control circuit coupled to provide a load signal; and

the latch circuits coupled to receive the load signal and provide the latched performance parameters in response to the load signal.

16. The device of claim 15, further including:

performance parameter adjusted circuits coupled to receive the latched performance parameters wherein

the performance parameter adjusted circuits have operational aspects adjusted in accordance with the values of the performance parameters.

17. The device of claim 15, further including:

a transition detector coupled to receive a least significant bit of the count value and provide a count transition pulse wherein

the control circuit is coupled to receive the count transition pulse, the control circuit provides the load signal in response to the count transition pulse.

18. A device, comprising:

a temperature circuit providing a plurality of temperature ranges, each temperature range having a temperature range upper limit value and a temperature range lower limit value, wherein adjacent ones of the plurality of temperature ranges overlap;

a power up circuit coupled to provide a power up signal in response to a transition in a power supply voltage; and

the temperature circuit is coupled to receive the power up signal, the temperature circuit is disabled in response to the power up signal.

19. A device, comprising:

a temperature circuit providing a plurality of temperature ranges, each temperature range having a temperature range upper limit value and a temperature range lower limit value, wherein adjacent ones of the plurality of temperature ranges overlap;

wherein

the temperature circuit includes a temperature sensor circuit that sets the temperature range upper limit value and the temperature range lower limit value.

20. The device of claim 19, wherein:

the temperature range lower limit value of an upper adjacent one of the temperature ranges is a lower temperature value than the temperature range upper limit value of a lower adjacent one of the temperature ranges.