Array substrate and manufacture method thereof, and touch display panel

• US 9,811,191 B2
• Filed: 08/04/2015
• Issued: 11/07/2017
• Est. Priority Date: 05/08/2015
• Status: Active Grant

• Current Assignee: Tianma Microelectronics Company Limited, Xiamen Tianma Micro-Electronics Co., Ltd.
• Original Assignee: Tianma Microelectronics Company Limited, Xiamen Tianma Micro-Electronics Co., Ltd.
• Inventors: Peng, Tao
• Primary Examiner(s): Vu, Phu
• Application Number:
  US14/818,292
• Publication Number:
  US 20160328058A1
• Time in Patent Office: 826 Days
• CPC Class Codes: G02F 1/13338 Input devices, e.g. touch panels
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G06F 2203/04103 Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods

Abstract

An array substrate, a manufacture method thereof and a touch display panel. The array substrate includes a base; a plurality of thin film transistors arranged in a matrix form, each of which including a gate electrode, a source electrode and a drain electrode; a first insulation layer located on the thin film transistor; a touch wiring layer which is disposed on the first insulation layer and includes a plurality of touch wirings; and a planarization layer covering the touch wiring layer. In some embodiments of the disclosure, the planarization layer covers the touch wiring layer, making the flatness over the touch wirings better, thus alleviating the light leakage at both sides of the touch wiring after the rubbing process.

Claims

1. An array substrate, comprising:

a base;

a plurality of thin film transistors arranged in a matrix form, each of which includes a gate electrode, a source electrode and a drain electrode;

a first insulation layer located on the thin film transistors;

a touch wiring layer which is disposed on the first insulation layer and comprises a plurality of touch wirings;

a planarization layer covering the touch wiring layer;

a common electrode layer located on the planarization layer and comprising a plurality of common electrodes, each of which is connected with one or more of the touch wirings and is operable as a touch sensing electrode;

a second insulation layer located on the common electrode layer; and

a pixel electrode layer which is located on the second insulation layer and comprises a plurality of pixel electrodes.

2. The array substrate of claim 1, wherein the planarization layer comprises a first via hole, through which the common electrode is connected with the touch wiring.

3. The array substrate of claim 1, wherein the planarization layer comprises a first via hole, through which the common electrode is directly connected with the touch wiring.

4. The array substrate of claim 2, wherein the second insulation layer comprises a second via hole aligning with the first via hole and a third via hole, and the common electrode is connected with the touch wiring through the first via hole, the second via hole and the third via hole.

5. The array substrate of claim 1, further comprising:

a plurality of scan lines extending along a first direction, which are located at the same layer as the gate electrode of the thin film transistor; and

a plurality of data lines, which are located at the same layer as the source electrode and the drain electrode of the thin film transistor and extend along a second direction intersecting the first direction, and an extending direction of the touch wirings is the same as that of the data lines.

6. The array substrate of claim 5, wherein the planarization layer comprises a first slot, which extends from the drain electrode of a thin film transistor to the drain electrode of an adjacent thin film transistor in the first direction.

7. The array substrate of claim 6, wherein the first slot penetrates through the planarization layer and the first insulation layer;

the common electrode layer extends into the first slot along the second direction to connect with the touch wiring;

only the touch wiring is covered with the common electrode layer within the first slot.

8. The array substrate of claim 7, wherein,

the second insulation layer covers a bottom of the first slot;

the second insulation layer further comprises a fourth via hole penetrating through the second insulation layer and located right above the drain electrode within a region of the first slot;

the pixel electrode layer extends into the fourth via hole to connect with the drain electrode along the first direction.

9. The array substrate of claim 8, wherein each of the pixel electrodes comprises at least two strip-shaped electrodes extending along the second direction.

10. The array substrate of claim 6, wherein two adjacent thin film transistors constitute a thin film transistor group, and two drain electrodes in the thin film transistor group correspond to the same first slot.

11. The array substrate of claim 1, wherein a thickness of the planarization layer is between 0.5 μ

m and 6 μ

m.

12. The array substrate of claim 1, wherein the first insulation layer is made of silicon oxide or silicon nitride.

13. The array substrate of claim 1, wherein the second insulation layer is made of silicon oxide or silicon nitride.

14. The array substrate of claim 1, wherein the thin film transistor further comprises an active layer made of amorphous silicon or low-temperature polycrystalline silicon.

15. A touch panel display, comprising the array substrate of claim 1, wherein the touch panel display further comprises a color filter substrate arranged opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate.

17. The array substrate of claim 1, wherein the planarization layer is made by an organic film.

16. A manufacture method of the array substrate, comprising:

forming a first metal layer on a base, and forming patterns of gate electrodes and scan lines on the first metal layer by a patterning process, wherein the scan lines extend along a first direction;

forming a third insulation layer on the first metal layer;

forming a second metal layer on the third insulation layer, and forming patters of source electrodes, drain electrodes and data lines on the second metal layer by the patterning process, wherein the data lines extend along a second direction intersecting the first direction;

forming a first insulation layer on the second metal layer;

forming a touch wiring layer on the first insulation layer, the touch wiring layer including a plurality of touch wirings extending along the second direction;

forming a planarization layer on the touch wiring layer;

forming a first slot on the planarization layer, the first slot extending from a drain electrode to an adjacent drain electrode in the first direction and penetrating through the planarization layer and the first insulation layer;

forming a common electrode layer on the planarization layer, and forming a plurality of common electrodes in the common electrode layer by the patterning process, wherein the common electrode layer extends into the first slot along the second direction to connect with the touch wiring, and only the touch wiring is covered with the common electrode layer within the first slot;

forming a second insulation layer on the common electrode layer, the second insulation layer covering a bottom of the first slot;

forming a fourth via hole in the second insulation layer, the fourth via hole being located right above the drain electrode within a region of the first slot and penetrating through the second insulation layer; and

forming a pixel electrode layer on the second insulation layer, the pixel electrode layer extending into the fourth via hole along the first direction to connect to the drain electrode.