Core ID designation system for dynamically designated bootstrap processor

• US 9,811,344 B2
• Filed: 11/21/2016
• Issued: 11/07/2017
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Stephan
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US15/357,145
• Publication Number:
  US 20170068546A1
• Time in Patent Office: 351 Days
• Field of Search: 710104-110, 710316-317, 713 1- 2, 713300-340
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to generate a default core ID and to sample the indicator. When the indicator indicates a first predetermined value, the default core ID generated by a default one of the plurality of processing cores designates the default processing core to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to generate alternate core IDs that are different from the default core IDs. One of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

Claims

1. A microprocessor, comprising:

an indicator; and

a plurality of processing cores, each configured to generate a default core ID number for itself, wherein each default core ID is unique;

wherein each of the plurality of processing cores is configured to sample the indicator;

wherein when the indicator indicates a first predetermined value, the default core ID generated by a default one of the processing cores designates the default processing core to be a bootstrap processor; and

wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are each configured to generate alternate core IDs that are different from the default core IDs, wherein one of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

2. The microprocessor of claim 1, wherein each processing core of the plurality of processing cores is configured to:

generate a distinct respective default interrupt controller identifier associated with the processing core; and

when the indicator indicates the second predetermined value, modify the associated default respective interrupt controller identifier such that each of the plurality of processing cores has a new distinct respective interrupt controller identifier.

3. The microprocessor of claim 1, wherein a holding register of the microprocessor comprises the indicator.

4. The microprocessor of claim 1, wherein the designated bootstrap processor fetches and executes instructions to bootstrap an operating system.

5. The microprocessor of claim 1, wherein the designated bootstrap processor fetches instructions at an architecturally-defined reset vector and executes the instructions.

6. The microprocessor of claim 1, wherein the designated bootstrap processor performs a package sleep state handshake protocol for the microprocessor, wherein none of the other plurality of processing cores performs the package sleep state handshake protocol.

7. The microprocessor of claim 2,

wherein the default core ID is the lowest-valued interrupt controller identifier of the processing cores;

and

wherein when the indicator indicates the second predetermined value, the bootstrap processor is designated by the lowest-valued modified interrupt controller identifier of the processing cores.

8. The microprocessor of claim 2, wherein to modify the default respective interrupt controller identifier associated with each of the plurality of processing cores, such that each of the plurality of processing cores has a new distinct respective interrupt controller identifier, the plurality of processing cores are configured to rotate the default respective interrupt controller identifiers among themselves.

9. The microprocessor of claim 2,

wherein the microprocessor comprises a plurality of semiconductor dies;

wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;

wherein the microprocessor is manufactured such that each of the plurality of processing cores has a predetermined die number and core number;

wherein for each processing core of the plurality of processing cores, to generate the distinct respective default interrupt controller identifier the processing core is configured to generate the distinct respective default interrupt controller identifier based on the predetermined die number and core number of the processing core.

10. The microprocessor of claim 3, wherein the holding register is configured to receive a sensed evaluation of a fuse that is either blown or unblown.

11. The microprocessor of claim 3, wherein the holding register is configured to receive a value of the indicator from a boundary scan input.

12. The microprocessor of claim 8, wherein to rotate the default respective interrupt controller identifier among the plurality of processing cores, the plurality of processing cores are configured to rotate by an amount specified by a second indicator of the microprocessor.

13. A method for configuring a multi-core microprocessor, the method comprising:

sampling an indicator of the microprocessor, wherein the microprocessor comprises a plurality of processing cores, each configured to generate a default core ID number for itself, wherein each default core ID is unique;

when the indicator indicates a first predetermined value;

the default core ID generated by a default one of the processing cores designates the default processing core to be a bootstrap processor; and

when the indicator indicates a second predetermined value distinct from the first predetermined value;

the plurality of processing cores each generate alternate core IDs that are different from the default core IDs, wherein one of the alternate core IDs designates an alternative processing core, other than the default processing core, to be the bootstrap processor.

14. The method of claim 13, further comprising:

generating a distinct respective default interrupt controller identifier associated with each of the plurality of processing cores; and

when the indicator indicates the second predetermined value, modifying the default respective interrupt controller identifier associated with each of the plurality of processing cores such that each of the plurality of processing cores has a new distinct respective interrupt controller identifier.

15. The method of claim 14, further comprising:

when the indicator indicates the first predetermined value, using the lowest-valued interrupt controller identifier of the processing cores to designate the bootstrap processor;

when the indicator indicates the second predetermined value, using the lowest-valued modified interrupt controller identifier of the processing cores to designate the bootstrap processor.

16. The method of claim 14, wherein said modifying the default respective interrupt controller identifier associated with each of the plurality of processing cores such that each of the plurality of processing cores has a new distinct respective interrupt controller identifier comprises rotating the default respective interrupt controller identifier among the plurality of processing cores.

17. The method of claim 14,

wherein the microprocessor comprises a plurality of semiconductor dies;

wherein a distinct subset of the plurality of processing cores is located on each of the plurality of semiconductor dies;

wherein the microprocessor is manufactured such that each of the plurality of processing cores has a predetermined die number and core number;

wherein for each processing core of the plurality of processing cores, said generating the distinct respective default interrupt controller identifier comprises generating the distinct respective default interrupt controller identifier based on the predetermined die number and core number of the processing core.

18. The method of claim 16, wherein said rotating the default respective interrupt controller identifier among the plurality of processing cores comprises rotating by an amount specified by a second indicator of the microprocessor.

19. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

first program code for specifying an indicator; and

second program code for specifying a plurality of processing cores, each configured to generate a default core ID number for itself,

wherein each default core ID is unique;

wherein each of the plurality of processing cores is configured to sample the indicator;

wherein when the indicator indicates a first predetermined value, the default core ID generated by a default one of the processing cores designates the default processing core to be a bootstrap processor; and

wherein when the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are each configured to generate alternate core IDs that are different from the default core IDs, wherein one of the alternate core IDs designates an alternate processing core, other than the default processing core, to be the bootstrap processor.

20. The computer program product of claim 19, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium.