Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)

• US 9,811,420 B2
• Filed: 03/27/2015
• Issued: 11/07/2017
• Est. Priority Date: 03/27/2015
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Das, Debaleena, Nale, Bill, Bains, Kuljit S, Halbert, John B
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/670,413
• Publication Number:
  US 20160283318A1
• Time in Patent Office: 956 Days
• CPC Class Codes: G06F 11/00 Error detection; Error correction; Monitoring error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/1084 Degraded mode, e.g. caused by single or multiple storage removals or disk failures

Abstract

Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Claims

1. A method for error correction in a memory subsystem, comprising:

performing internal error detection in a memory device to detect errors in read data in response to a read request from an associated memory controller, the internal error detection to be performed with internal check bits generated within the memory device;

selectively performing an internal error correction operation on the read data in response to detecting an error in the read data with the internal check bits;

generating check bits indicating an error vector for the read data to compare against the internal check bits for performing the internal error detection and correction; and

providing the check bits with the read data to the associated memory controller in response to the read request, the check bits for use by the associated memory controller in additional error correction external to the memory device.

2. The method of claim 1, wherein generating the check bits indicating the error vector further comprises generating an error vector indicating no errors in response to detecting no errors in the read data.

3. The method of claim 1, wherein generating the check bits indicating the error vector further comprises generating an error vector indicating no errors in response to detecting a single bit error in the read data, wherein the internal error correction operation further comprises performing single bit error correction.

4. The method of claim 1, wherein generating the check bits indicating the error vector further comprises generating an error vector indicating an uncorrected error in response to detecting a multibit error in the read data, wherein the internal error correction operation further comprises detecting the multibit error.

5. The method of claim 1, wherein providing the check bits with the read data comprises providing the check bits as metadata for a single device data correction (SDDC) error checking and correction (ECC) operation performed by the associated memory controller on the read data in connection with parallel read data from an additional memory device.

6. The method of claim 1, wherein providing the check bits further comprises selectively providing the check bits in response to a logic value of an address bit in a Read column address strobe (CAS) command issued by the associated memory controller.

7. A memory device that applies internal error correction, comprising:

an error detection circuit to perform internal error detection in a memory device to detect errors in read data in response to a read request from an associated memory controller, the internal error detection to be performed with internal check bits generated within the memory device;

an error correction circuit to selectively perform an internal error correction operation on the read data in response to detection of an error in read data with the internal check bits, and generate check bits to indicate an error vector for the read data to compare against the internal check bits for performance internal error detection and correction; and

I/O (input/output) hardware to transmit the check bits with the read data to the associated memory controller in response to the read request, the check bits for use by the associated memory controller in additional error correction external to the memory device.

8. The memory device of claim 7, wherein the error correction circuit is to generate an error vector to indicate no errors in response to detection of no errors in the read data.

9. The memory device of claim 7, wherein the error correction circuit is to generate an error vector to indicate no errors in response to detection of a single bit error in the read data, wherein internal error correction operation further comprises performance of single bit error correction.

10. The memory device of claim 7, wherein the error correction circuit is to generate an error vector to indicate an uncorrected error in response to detection of a multibit error in the read data, wherein internal error correction operation further comprises detection of the multibit error.

11. The memory device of claim 7, wherein the I/O hardware is to provide the read data with the check bits as metadata for a single device data correction (SDDC) error checking and correction (ECC) operation performed by the associated memory controller on the read data in connection with parallel read data from an additional memory device.

12. The memory device of claim 7, wherein the I/O hardware is to selectively provide the check bits in response to a logic value of an address bit in a Read column address strobe (CAS) command issued by the associated memory controller.

13. An electronic device with a memory subsystem, comprising:

a memory controller to generate a Read command to read data from associated memory devices, the Read command including a request for internal check bits from an internal error correction operation performed at the associated memory devices in response to the Read command;

multiple DRAM (dynamic random access memory) devices each including a memory array of addressable memory locations, wherein the memory arrays are addressable according to multiple different levels of granularity, the DRAM devices including

an error detection circuit to perform internal error detection to detect errors in read data in response to the Read command, the internal error detection to be performed with internal check bits generated within the DRAM device;

an error correction circuit to selectively perform an internal error correction operation on the read data in response to detection of an error in read data with the internal check bits, and generate check bits to indicate an error vector for the read data to compare against the internal check bits for performance of internal error detection and correction; and

I/O (input/output) hardware to transmit the check bits with the read data to the memory controller in response to the Read command including the request for internal check bits;

wherein the memory controller is to access the check bits for additional error correction external to the DRAM devices; and

a chassis system to couple the memory subsystem to a blade server.

14. The electronic device of claim 13, wherein the memory controller further includes C/A logic to generate a Read column address strobe (CAS) command with a logic value to indicate the DRAM device to send the check bits.

15. The electronic device of claim 13, wherein DRAM error correction logic is to generate an error vector to indicate an uncorrected error in response to detection of a multibit error in the read data.

16. The electronic device of claim 13, wherein the memory controller further includes error correction logic to access the check bits as metadata for a single device data correction (SDDC) error checking and correction (ECC) operation performed on the read data in connection with parallel read data from an additional memory device.