Radix table translation of memory

• US 9,811,472 B2
• Filed: 06/14/2012
• Issued: 11/07/2017
• Est. Priority Date: 06/14/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bybell, Anthony J., Gschwind, Michael K.
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Assistant Examiner(s): Westbrook, Michael
• Application Number:
  US13/517,758
• Publication Number:
  US 20130339652A1
• Time in Patent Office: 1,972 Days
• Field of Search: 711205-208
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1018 involving hashing techniques, e.g. inverted page tables
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence

Abstract

Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.

Claims

1. A computer program product for accessing a memory location in a processing system, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

receiving a request to access a desired block of memory located in one of a plurality of non-contiguous virtual memory regions, the request comprising an effective address consisting of an effective segment identifier (ESID) and a linear address, the linear address consisting of a most significant portion and a byte index;

locating, by a processor, an entry corresponding to the effective address in a segment lookaside buffer (SLB) that includes multiple entries that include radix page table pointers (RPTPs) corresponding to the plurality of non-contiguous virtual memory regions; and

based on the located entry corresponding to the effective address in the SLB including an RPTP corresponding to the one of the plurality of non-contiguous virtual memory regions, performing;

using the RPTP from the located entry to locate a translation table of a hierarchy of translation tables;

using the located translation table to translate the entirety of the most significant portion of the linear address to obtain an address of a block of memory; and

based on the obtained address, performing the requested access to the desired block of memory.

2. The computer program product of claim 1, further comprising using the byte index of the linear address and the obtained address to form an address of the desired block of memory.

3. The computer program product of claim 1, wherein a table level of the located translation table of the hierarchy of translation tables is indicated by the RPTP.

4. The computer program product of claim 1, wherein the RPTP specifies a size of the linear address.

5. The computer program product of claim 1, wherein a portion of the linear address is used to index into the located translation table to locate a translation table entry, the translation table entry comprising an origin address of a next level translation table of the hierarchy of translation tables.

6. The computer program product of claim 1, wherein the linear address includes a page identifier and a byte offset identifier.

7. The computer program product of claim 1, wherein locating the entry corresponding to the effective address in the SLB comprises:

selecting a first valid entry in the SLB;

extracting a segment size from the first valid entry;

calculating an ESID mask of the first valid entry based on the extracted segment size;

determining whether an ESID of the first valid entry corresponds to the ESID of the effective address based on the ESID mask;

based on determining that the ESID mask of the first valid entry corresponds to the ESID of the effective address, determining that the first valid entry is the located entry corresponding to the effective address in the SLB; and

based on determining that the ESID mask of the first valid entry does not correspond to the ESID of the effective address, determining that the first valid entry is not the entry corresponding to the effective address in the SLB, and selecting a next valid entry in the SLB.

8. The computer program product of claim 1, wherein, in the effective address, the ESID is located adjacent to and before the most significant portion of the linear address, and the most significant portion of the linear address is located adjacent to and before the byte index of the linear address.

9. A computer system for accessing a memory location, the system comprising:

a memory; and

a processor configured to perform a method comprising;

receiving a request to access a desired block of memory located in one of a plurality of non-contiguous virtual memory regions, the request comprising an effective address consisting of an effective segment identifier (ESID) and a linear address, the linear address consisting of a most significant portion and a byte index;

locating, by a processor, an entry corresponding to the effective address in a segment lookaside buffer (SLB) that includes multiple entries that include radix page table pointers (RPTPs) corresponding to the plurality of non-contiguous virtual memory regions; and

based on the located entry corresponding to the effective address in the SLB including an RPTP corresponding to the one of the plurality of non-contiguous virtual memory regions, performing;

using the RPTP from the located entry to locate a translation table of a hierarchy of translation tables;

using the located translation table to translate the entirety of the most significant portion of the linear address to obtain an address of a block of memory; and

based on the obtained address, performing the requested access to the desired block of memory.

10. The system of claim 9, further comprising using the byte index of the linear address and the obtained address to form an address of the desired block of memory.

11. The system of claim 9, wherein a table level of the located translation table of the hierarchy of translation tables is indicated by the RPTP.

12. The system of claim 9, wherein the RPTP specifies a size of the linear address.

13. The system of claim 9, wherein a portion of the linear address is used to index into the located translation table to locate a translation table entry, the translation table entry comprising an origin address of a next level translation table of the hierarchy of translation tables.

14. The system of claim 9, wherein locating the entry corresponding to the effective address in the SLB comprises:

selecting a first valid entry in the SLB;

extracting a segment size from the first valid entry;

calculating an ESID mask of the first valid entry based on the extracted segment size;

determining whether an ESID of the first valid entry corresponds to the ESID of the effective address based on the ESID mask;

based on determining that the ESID mask of the first valid entry corresponds to the ESID of the effective address, determining that the first valid entry is the located entry corresponding to the effective address in the SLB; and

based on determining that the ESID mask of the first valid entry does not correspond to the ESID of the effective address, determining that the first valid entry is not the entry corresponding to the effective address in the SLB, and selecting a next valid entry in the SLB.

15. The system of claim 9, wherein, in the effective address, the ESID is located adjacent to and before the most significant portion of the linear address, and the most significant portion of the linear address is located adjacent to and before the byte index of the linear address.