Storage unit controller and control method thereof, and storage device

• US 9,811,473 B2
• Filed: 09/04/2014
• Issued: 11/07/2017
• Est. Priority Date: 04/22/2014
• Status: Active Grant

• Current Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Original Assignee: Nuvoton Technology Corporation (Winbond Electronics Corporation)
• Inventors: Lu, Chia-Ching
• Primary Examiner(s): Bataille, Pierre-Michel
• Application Number:
  US14/476,758
• Publication Number:
  US 20150301944A1
• Time in Patent Office: 1,160 Days
• Field of Search: 711156, 711143
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping

Abstract

A storage unit controller and a control method thereof, and a storage device are provided. The storage unit controller includes an address mapping unit, a nonvolatile buffer and an update indicator. The update indicator sets an indicated flag according to whether a first data saved in the nonvolatile buffer is written to a storage unit. The address mapping unit checks the indicated flag when power is on. When the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode so as to perform background operations: the first data has not yet been successfully addressed to the storage unit previously, but saved in a simulated address of the nonvolatile buffer to transfer the first data from the simulated address to an actual address of the storage unit.

Claims

1. A method for controlling a storage unit comprising a nonvolatile memory, comprising:

setting an indicated flag according to whether a first data saved in a nonvolatile buffer is written to a storage unit;

checking the indicated flag when power is on; and

enabling an update operation mode when the checked indicated flag indicates that the first data is not completed, wherein enabling the update operation mode at least executes;

transferring the first data saved at a simulated address of the nonvolatile buffer from the simulated address to a first actual address of the storage unit,

wherein the nonvolatile buffer comprises;

a first buffer unit for saving the first data at the simulated address of the first buffer unit in a process in which the first data is addressed; and

a second buffer unit coupled to the first buffer unit, wherein the second buffer acts as a read buffer of the storage unit, and used as a write backup buffer of the first buffer unit when the first buffer unit is under the update operation mode.

2. The method for controlling the storage unit according to claim 1, wherein, when the checked indicated flag indicates that writing the first data is not completed while a host is to read the first data, the first data located at the simulated address is transmitted to the host.

3. The method for controlling the storage unit according to claim 1, wherein the first data is transferred from the simulated address to the first actual address of the storage unit under the update operation mode.

4. The method for controlling the storage unit according to claim 1, wherein, when the first buffer unit is under the update operation mode while a host is to write a second data, the second data is addressed at a second actual address of the storage unit via the second buffer unit.

5. The method for controlling the storage unit according to claim 1, wherein, when the first buffer unit is under the update operation mode while a host is to read a third data saved in the storage unit via the storage unit controller, the third data is read via the second buffer unit.

6. A storage unit controller, comprising:

an address mapping unit;

a nonvolatile buffer coupled to the address mapping unit; and

an update indicator coupled to the address mapping unit and the nonvolatile buffer, and the update indicator setting an indicated flag according to whether a first data saved in the nonvolatile buffer is written to a storage unit;

wherein the address mapping unit checks the indicated flag when power is on, when the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode, and enabling the update operation mode at least comprises;

transferring the first data saved at a simulated address of the nonvolatile buffer from the simulated address to a first actual address of the storage unit,

wherein the nonvolatile buffer comprises;

a first buffer unit coupled to the address mapping unit and the update indicator, wherein the first data is initially saved at the simulated address of the first buffer unit during a process in which the address mapping unit addresses the first data; and

a second buffer unit coupled to the address mapping unit, the update indicator and the first buffer unit, wherein the second buffer unit acts as a read buffer of the storage unit and used as a write backup buffer of the first buffer unit when the first buffer unit is under the update operation mode.

7. The storage unit controller according to claim 6, wherein, when the checked indicated flag indicates that writing the first data is not completed while a host is to read the first data via the storage unit controller, the address mapping unit transmits the first data at the simulated address to the host.

8. The storage unit controller according to claim 6, wherein the nonvolatile buffer is a resistive random access memory (RRAM), a magnetoresistance random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), or a conductive bridge random access memory (CBRAM).

9. The storage unit controller according to claim 6, wherein the address mapping unit transfers the first data from the simulated address to the first actual address of the storage unit under the update operation mode.

10. The storage unit controller according to claim 6, wherein, when the first buffer unit is in the update operation process while a host writes a second data via the storage unit controller, the address mapping unit addresses the second data to a second actual address of the storage unit via the second buffer unit.

11. The storage unit controller according to claim 6, wherein, when the first buffer unit is under the update operation mode while a host is to read a third data saved in the storage unit via the storage unit controller, the third data is read via the second buffer unit.

12. The storage unit controller according to claim 6, further comprising:

a status register coupled to the update indicator and the address mapping unit, and the status register generating a busy status information under the update operation mode according to the indicated flag.

13. The storage unit controller according to claim 6, wherein a speed of the first data written to the simulated address of nonvolatile buffer is faster than a speed of the first data written to the first actual address of the storage unit.

14. A storage device, comprising:

a storage unit;

a nonvolatile buffer coupled to the storage unit;

an address mapping unit coupled to the nonvolatile buffer, the address mapping unit performs addressing before a first data is written to the nonvolatile buffer so as to provide a simulated address corresponding to the first actual address and record the simulated address; and

an update indicator coupled to the nonvolatile buffer and the address mapping unit, and the update indicator sets an indicated flag according to whether the first data saved in the nonvolatile buffer is written to the storage unit,

wherein the address mapping unit checks the indicated flag when power is on, when the checked indicated flag indicates that writing the first data is not completed, the address mapping unit enables an update operation mode to enter the update operation mode so as to transfer the first data saved in the nonvolatile buffer but not completely written to the storage unit from the simulated address to a first actual address of the storage unit,

wherein, when a host is to write the first data to the storage unit, the first data is written to the simulated address of the nonvolatile buffer, and then the first data is written to the first actual address of the storage unit from the simulated address.

15. The storage device according to claim 14, wherein the first data not completely written to the storage unit is saved in the nonvolatile buffer when power is off, and the first data is not lost after the power is off.

16. The storage device according to claim 14, wherein the address mapping unit receives a write command from the host, and writes the first data to the simulated address, then the address mapping unit transfers the first data from the simulated address to the first actual address.

17. The storage device according to claim 14, wherein, when the checked indicated flag indicates that writing the first data is not completed while a host is to read the first data via the storage device, the storage device transmitted the first data at the simulated address to the host via the address mapping unit.

18. The storage device according to claim 14, wherein the storage unit is an NAND flash memory, an exclusive NOR flash memory, a resistive random access memory (RRAM), a magnetoresistance random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change random access memory (PRAM), a conductive bridge random access memory (CBRAM), a solid state disk or a storage sector in a hard disk.

19. The storage device according to claim 14, wherein the nonvolatile buffer comprises:

a first buffer unit coupled to the address mapping unit and the update indicator; and

a second buffer unit coupled to the address mapping unit, the update indicator and the first buffer unit, wherein the second buffer unit acts as a read buffer of the storage unit, and used as a write backup buffer of the first buffer unit when the first buffer unit is under the update operation mode.