Semiconductor device

• US 9,811,493 B2
• Filed: 09/02/2015
• Issued: 11/07/2017
• Est. Priority Date: 05/29/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kojima, Masatsugu, Abe, Mitsuhiro
• Primary Examiner(s): Shin, Christopher
• Application Number:
  US14/843,497
• Publication Number:
  US 20160350253A1
• Time in Patent Office: 797 Days
• Field of Search: 710310, 710312, 710 58
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus

Abstract

According to one embodiment, a semiconductor device includes an input/output circuit. An input/output circuit includes first to third circuits. The first circuit transmits one of first to third data to the second circuit. The second circuit outputs the data, in a first-in-first-out (FIFO) format. The third circuit transmits first clock signal to the first circuit when the first circuit outputs one of the first and second data. When the one of the first and second data is read, the second circuit receives the one of the first and second data in response to the first clock signal within a period until a first signal is received. When the third data is read, the second circuit receives the third data in response to a second clock signal within the period.

Claims

1. A semiconductor device comprising:

a memory;

a data register coupled to the memory;

an input/output circuit coupled to the data register and configured to input and output data to and from an external controller which issues and transmits a command to the device,

wherein the input/output circuit includes;

a first clock generator configured to generate a first clock signal and transmit the first clock signal to a first signal line,

a first selector configured to receive first data from a first bus, receive second data from a second bus, and transmit one of the first and second data to a third bus,

a second selector configured to receive the one of the first and second data from the third bus, receive third data from a fourth bus, receive the first clock signal corresponding to the first and second data from the first signal line, receive a second clock signal corresponding to the third data from a second signal line, transmit one of the first to third data to a fifth bus, and transmit one of the first and second clock signals to a third signal line; and

a first-in-first-out (FIFO) circuit configured to receive the one of the first to third data from the fifth bus and receive the one of the first and second clock signals from the third signal line,

when a read operation of the one of the first and second data is executed, the FIFO circuit receives the one of the first and second data in response to the first clock signal within a period from when a read command and address data are received until a read enable signal is received from the external controller, and

when a read operation of the third data is executed, the FIFO circuit receives the third data in response to the second clock signal within the period.

2. The device according to claim 1, wherein

the input/output circuit further includes:

second clock generator configured to generate third and fourth clock signals which are mutually opposite-phase and synchronized with each other, based on the read enable signal; and

an output register configured to output the one of the first to third data which is received from the FIFO circuit in response to the third and/or fourth clock signal which is received from the second clock generator.

3. The device according to claim 1, wherein

the first and second selectors receive a first data enable signal and a second data enable signal,

when the first data enable signal is at a first logic level, the first selector transmits the first data to the second selector, and the second selector transmits the first data and the first clock signal to the FIFO circuit,

when the second data enable signal is at the first logic level, the first selector transmits the second data to the second selector, and the second selector transmits the second data and the first clock signal to the FIFO circuit, and

when neither the first data enable signal nor the second data enable signal are at the first logic level, the second selector transmits the third data and the second clock signal to the FIFO circuit.

4. The device according to claim 1, wherein

the FIFO circuit ends the receiving of the one of the first and second data within the period.

5. The device according to claim 1,

wherein the first data includes identification data of the device,

the second data includes parameter data of the device, and

the third data includes data stored in the memory.

6. The device according to claim 2, wherein

the output register receives the one of the first to third data within the period.

7. The device according to claim 2, wherein

the input/output circuit further includes a FIFO controller configured to control the FIFO circuit,

the FIFO circuit includes a plurality of internal registers configured to hold the first to third data,

the FIFO controller includes:

an input address register configured to hold input addresses of the internal registers which received the one of the first to third data from the second selector; and

an output address register configured to hold output addresses of the internal registers which transmit the one of the first to third data to the output register, and

the FIFO controller resets the input addresses held by the input address register and the output addresses held by the output address register according to the reception of the read command or the address data.

8. The device according to claim 2, wherein

the input/output circuit further includes a third selector coupled to the FIFO circuit through sixth and seventh buses and coupled to the output register through eighth and ninth buses,

when the third selector receives the first data from the FIFO circuit through the sixth and seventh buses, the third selector transmits the received first data to the output register through the eighth bus,

when the third selector receives the second data from the FIFO circuit through the sixth and seventh buses, the third selector transmits the received second data to the output register through the ninth bus, and

when the third selector receives the third data from the FIFO circuit through the sixth and seventh buses, the third selector transmits the third data received from the sixth bus to the output register through the eighth bus and transmits the third data received from the seventh bus to the output register through the ninth bus.

9. The device according to claim 2, wherein,

in the reading operation of the first data, the output register outputs the first data according to a falling timing of the read enable signal.

10. The device according to claim 2, wherein,

in the reading operation of the second data, the output register outputs the second data according to a rising timing of the read enable signal.

11. The device according to claim 3, wherein

the first bus includes first and second data lines,

the third bus includes a third data line,

the first clock generator supplies data select signal to the first selector, and

the first selector switches a connection of the first and second data lines with the third data line in response to the data select signal.

12. The device according to claim 7, wherein

the second clock generator is configured to generate a fifth clock signal based on the read enable signal, and

the FIFO controller determines the input addresses in response to one of the first and second clock signals and determines the output addresses in response to the fifth clock signal.