Semiconductor device
First Claim
1. A semiconductor device comprising:
- a memory;
a data register coupled to the memory;
an input/output circuit coupled to the data register and configured to input and output data to and from an external controller which issues and transmits a command to the device,wherein the input/output circuit includes;
a first clock generator configured to generate a first clock signal and transmit the first clock signal to a first signal line,a first selector configured to receive first data from a first bus, receive second data from a second bus, and transmit one of the first and second data to a third bus,a second selector configured to receive the one of the first and second data from the third bus, receive third data from a fourth bus, receive the first clock signal corresponding to the first and second data from the first signal line, receive a second clock signal corresponding to the third data from a second signal line, transmit one of the first to third data to a fifth bus, and transmit one of the first and second clock signals to a third signal line; and
a first-in-first-out (FIFO) circuit configured to receive the one of the first to third data from the fifth bus and receive the one of the first and second clock signals from the third signal line,when a read operation of the one of the first and second data is executed, the FIFO circuit receives the one of the first and second data in response to the first clock signal within a period from when a read command and address data are received until a read enable signal is received from the external controller, andwhen a read operation of the third data is executed, the FIFO circuit receives the third data in response to the second clock signal within the period.
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Accused Products
Abstract
According to one embodiment, a semiconductor device includes an input/output circuit. An input/output circuit includes first to third circuits. The first circuit transmits one of first to third data to the second circuit. The second circuit outputs the data, in a first-in-first-out (FIFO) format. The third circuit transmits first clock signal to the first circuit when the first circuit outputs one of the first and second data. When the one of the first and second data is read, the second circuit receives the one of the first and second data in response to the first clock signal within a period until a first signal is received. When the third data is read, the second circuit receives the third data in response to a second clock signal within the period.
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Citations
12 Claims
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1. A semiconductor device comprising:
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a memory; a data register coupled to the memory; an input/output circuit coupled to the data register and configured to input and output data to and from an external controller which issues and transmits a command to the device, wherein the input/output circuit includes; a first clock generator configured to generate a first clock signal and transmit the first clock signal to a first signal line, a first selector configured to receive first data from a first bus, receive second data from a second bus, and transmit one of the first and second data to a third bus, a second selector configured to receive the one of the first and second data from the third bus, receive third data from a fourth bus, receive the first clock signal corresponding to the first and second data from the first signal line, receive a second clock signal corresponding to the third data from a second signal line, transmit one of the first to third data to a fifth bus, and transmit one of the first and second clock signals to a third signal line; and a first-in-first-out (FIFO) circuit configured to receive the one of the first to third data from the fifth bus and receive the one of the first and second clock signals from the third signal line, when a read operation of the one of the first and second data is executed, the FIFO circuit receives the one of the first and second data in response to the first clock signal within a period from when a read command and address data are received until a read enable signal is received from the external controller, and when a read operation of the third data is executed, the FIFO circuit receives the third data in response to the second clock signal within the period. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification