Timing closure methodology including placement with initial delay values

• US 9,811,624 B2
• Filed: 12/16/2013
• Issued: 11/07/2017
• Est. Priority Date: 12/24/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation, Synopsys Incorporated
• Original Assignee: International Business Machines Corporation, Synopsys Incorporated
• Inventors: van Ginneken, Lukas P. P. P., Kudva, Prabhakar
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US14/108,243
• Publication Number:
  US 20140109034A1
• Time in Patent Office: 1,422 Days
• Field of Search: 716104, 716113, 716118, 716119, 716123, 716132, 716133, 716135
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/27 using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path.

Claims

1. An electronic design automation tool executing, on a computer, an automated method for designing an electronic circuit to manufacture that is area-optimized, the method comprising:

configuring a host computer system comprising a microprocessor and a memory that stores an electronic circuit description and a cell library comprising a plurality of discrete electrical circuit component cells, the microprocessor configured to;

generate a netlist of a plurality of implementations of the electronic circuit description, each implementation comprising an arrangement of cells;

calculate, for each implementation of the electronic circuit description, a net weight describing a sensitivity of an area of the implementation to variations in load;

map an electronic circuit layout according to the implementation of the circuit associated with a lowest net weight, the map of the electronic circuit layout corresponding to the implementation having a lowest sensitivity for the electronic circuit; and

adjust a gate size of a cell of the mapped electronic circuit layout in a design to manufacture the electronic circuit, the gate size meeting one or more timing requirements associated with the electronic circuit.

2. The method of claim 1, wherein the sensitivity indicates sensitivity of area of an implementation with respect to variations in load on a cell.

3. The method of claim 1, wherein the sensitivity indicates sensitivity of area of an implementation with respect to variations in load of a particular net.

4. An automated method for designing an area-optimized circuit to manufacture with a computer, comprising:

calculating, using a computer, for each implementation of the circuit, a net weight describing a sensitivity of an area to variations in load; and

selecting, during layout of the circuit, an implementation to manufacture the circuit, the implementation having a lowest net weight;

wherein the net weight is determined according to the following;

wi=dA/dCi=da/dCi+sum wj*(1/hij), where the subscript j represents a fanin gate of a given gate i in the implementation, the parameter wi is the net weight of the gate i, A is a total area of the implementation, ai is the area of the gate i, Ci is capacitive load of the gate i and hij is electrical effort between gates i and j.

5. A non-transitory computer readable storage medium storing instructions to design to manufacture an area-optimized circuit, the instructions comprising instructions that when executed cause a processor to:

calculate, for each implementation of the circuit, a net weight describing a sensitivity of an area to variations in load; and

select, during layout of the circuit, an implementation to manufacture the circuit, the implementation having a lowest net weight;

wherein said sensitivity comprises net weight determined according to the following;

wi=dA/dCi=da/dCi+sum wj*(1/hij), where the subscript j represents a fanin gate of a given gate i in the implementation, the parameter wi is the net weight of the gate i, A is a total area of the implementation, ai is the area of the gate i, Ci is capacitive load of the gate i and hij is electrical effort between gates i and j.

6. A non-transitory computer-readable storage medium storing instructions of an electronic design automation tool for designing an electronic circuit to manufacture that is area-optimized, the instructions when executed causing a processor to:

generate a netlist of a plurality of implementations of an electronic circuit description, each implementation comprising an arrangement of cells;

calculate, for each implementation of the electronic circuit description, a net weight describing a sensitivity of an area of the implementation to variations in load;

map an electronic circuit layout according to the implementation of the circuit associated with a lowest net weight, the map of the electronic circuit layout corresponding to the implementation having a lowest sensitivity for the electronic circuit; and

adjust a gate size of a cell of the mapped electronic circuit layout in a design to manufacture the electronic circuit, the gate size meeting one or more timing requirements associated with the electronic circuit.

7. The computer-readable storage medium of claim 6, wherein the sensitivity indicates sensitivity of an area of an implementation with respect to variations in load on a cell.

8. The computer-readable storage medium of claim 6, wherein the sensitivity indicates sensitivity of an area of an implementation with respect to variations in load of a particular net.

9. A computer system comprising:

at least one processor; and

a memory storing instructions that when executed by the processor cause the processor to;

generate a netlist of a plurality of implementations of an electronic circuit description, each implementation comprising an arrangement of cells;

calculate, for each implementation of the electronic circuit description, a net weight describing a sensitivity of an area of the implementation to variations in load;

map an electronic circuit layout according to the implementation of the circuit associated with a lowest net weight, the map of the electronic circuit layout corresponding to the implementation having a lowest sensitivity for the electronic circuit; and

adjust, within the mapped electronic circuit layout in a design to manufacture the electronic circuit, a gate size of a cell to meet one or more timing requirements associated with the mapped circuit implementation.