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Chip ID generation using physical unclonable function

  • US 9,811,689 B1
  • Filed: 12/27/2016
  • Issued: 11/07/2017
  • Est. Priority Date: 12/27/2016
  • Status: Active Grant
First Claim
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1. A method for generating a data set on an integrated circuit including programmable resistance memory cells, comprising:

  • applying a forming pulse to all members of a set of the programmable resistance memory cells, the forming pulse having a forming pulse level characterized by inducing a change in resistance in a first subset of the set of programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set of programmable resistance memory cells has a resistance outside the intermediate resistance range; and

    applying a programming pulse to the first and second subsets of programmable resistance memory cells, the programming pulse having a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate resistance range to a first final resistance range, while after the programming pulse the second subset of programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range, whereby the first and second subsets of the set of programmable memory cells store said data set.

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