Chip ID generation using physical unclonable function
First Claim
1. A method for generating a data set on an integrated circuit including programmable resistance memory cells, comprising:
- applying a forming pulse to all members of a set of the programmable resistance memory cells, the forming pulse having a forming pulse level characterized by inducing a change in resistance in a first subset of the set of programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set of programmable resistance memory cells has a resistance outside the intermediate resistance range; and
applying a programming pulse to the first and second subsets of programmable resistance memory cells, the programming pulse having a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate resistance range to a first final resistance range, while after the programming pulse the second subset of programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range, whereby the first and second subsets of the set of programmable memory cells store said data set.
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Abstract
A method for generating a data set on an integrated circuit including programmable resistance memory cells includes applying a forming pulse to all members of a set of the programmable resistance memory cells. The forming pulse has a forming pulse level characterized by inducing a change in resistance in a first subset of the set from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set has a resistance outside the intermediate range. The method includes applying a programming pulse to the first and second subsets. The programming pulse has a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate range to a first final range, while after the programming pulse the second subset has a resistance in a second final range, whereby the first and second subsets store said data set.
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Citations
19 Claims
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1. A method for generating a data set on an integrated circuit including programmable resistance memory cells, comprising:
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applying a forming pulse to all members of a set of the programmable resistance memory cells, the forming pulse having a forming pulse level characterized by inducing a change in resistance in a first subset of the set of programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set of programmable resistance memory cells has a resistance outside the intermediate resistance range; and applying a programming pulse to the first and second subsets of programmable resistance memory cells, the programming pulse having a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate resistance range to a first final resistance range, while after the programming pulse the second subset of programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range, whereby the first and second subsets of the set of programmable memory cells store said data set. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing an integrated circuit, comprising:
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forming a plurality of programmable resistance memory cells on the integrated circuit; connecting the integrated circuit to a system configured to apply a physical unclonable function to programmable resistance memory cells on the integrated circuit, and using the system, to generate a data set in a set of programmable resistance memory cells in the plurality of programmable resistance memory cells, by; applying a forming pulse to all members of the set, the forming pulse having a forming pulse level characterized by inducing a change in resistance in a first subset of the set of programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set of programmable resistance memory cells has a resistance outside the intermediate resistance range; and applying a programming pulse to the first and second subsets of programmable resistance memory cells, the programming pulse having a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate resistance range to a first final resistance range, while after the programming pulse the second subset of programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range, whereby the first and second subsets of the set of programmable memory cells store said data set. - View Dependent Claims (11, 12, 13, 14)
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15. An apparatus, comprising:
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a plurality of programmable resistance memory cells; and a controller configured, to generate a data set in a set of programmable resistance memory cells in the plurality of programmable resistance memory cells, by a procedure including; applying a forming pulse to all members of the set, the forming pulse having a forming pulse level characterized by inducing a change in resistance in a first subset of the set of programmable resistance memory cells from an initial resistance range to an intermediate resistance range, while after the forming pulse a second subset of the set of programmable resistance memory cells has a resistance outside the intermediate resistance range; and applying a programming pulse to the first and second subsets of programmable resistance memory cells, the programming pulse having a programming pulse level characterized by inducing a change in resistance of the first subset from the intermediate resistance range to a first final resistance range, while after the programming pulse the second subset of programmable resistance memory cells has a resistance in a second final resistance range that does not overlap the first final resistance range, whereby the first and second subsets of the set of programmable memory cells store said data set. - View Dependent Claims (16, 17, 18, 19)
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Specification