Semiconductor device

• US 9,812,178 B2
• Filed: 03/15/2016
• Issued: 11/07/2017
• Est. Priority Date: 03/07/2012
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/070,145
• Publication Number:
  US 20160196854A1
• Time in Patent Office: 602 Days
• Field of Search: 365227, 365228
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785

Abstract

To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch.

Claims

1. A semiconductor device comprising:

an arithmetic circuit;

a memory circuit configured to hold data obtained by the arithmetic circuit;

a power supply control switch configured to control whether a power supply voltage is supplied to the arithmetic circuit or not; and

a temperature detection circuit configured to detect a temperature of the memory circuit and to estimate an amount of an extra power consumed at a time of writing the data to the memory circuit and a time of reading the data from the memory circuit from the temperature,

wherein the power supply control switch is configured to be turned off so as not to supply the power supply voltage to the arithmetic circuit during a period, when a power consumption of the arithmetic circuit during the period is larger than the extra power consumed at a time of writing the data to the memory circuit and a time of reading the data from the memory circuit.

2. The semiconductor device according to claim 1, wherein the memory circuit comprises a transistor in which a channel formation region comprises an oxide semiconductor.

3. The semiconductor device according to claim 1, wherein the power supply control switch comprises a transistor in which a channel formation region comprises an oxide semiconductor.

4. The semiconductor device according to claim 1,

wherein the supply of the power supply voltage to the arithmetic circuit is controlled by a transistor in the power supply control switch.

5. A semiconductor device comprising:

an arithmetic circuit;

a first memory circuit configured to hold first data obtained by the arithmetic circuit;

a cache memory;

a second memory circuit configured to hold second data stored in the cache memory;

a first power supply control switch configured to control whether a power supply voltage is supplied to the arithmetic circuit or not;

a second power supply control switch configured to control whether a power supply voltage is supplied to the cache memory or not;

a temperature detection circuit configured to detect a first temperature of the first memory circuit and to estimate an amount of a first extra power consumed at a time of writing the first data to the first memory circuit and a time of reading the first data from the first memory circuit from the first temperature, and configured to detect a second temperature of the second memory circuit to estimate an amount of a second extra power consumed at a time of writing the second data to the second memory circuit and a time of reading the second data from the second memory circuit from the second temperature,

wherein the first power supply control switch is configured to be turned off so as not to supply the power supply voltage to the arithmetic circuit during a first period, when a power consumption of the arithmetic circuit during the first period is larger than the first extra power, and

wherein the second power supply control switch is configured to be turned off so as not to supply the power supply voltage to the cache memory during a second period, when a power consumption of the cache memory during the second period is larger than the second extra power.

6. The semiconductor device according to claim 5, wherein the first memory circuit comprises a transistor in which a channel formation region comprises an oxide semiconductor.

7. The semiconductor device according to claim 5, wherein at least one of the first power supply control switch and the second power supply control switch comprises a transistor in which a channel formation region comprises an oxide semiconductor.

8. The semiconductor device according to claim 5, wherein the supply of the power supply voltage to one or both of the arithmetic circuit and the cache memory is controlled by a transistor in the first power supply control switch.

9. A semiconductor device comprising:

an arithmetic circuit;

a first memory circuit configured to hold first data obtained by the arithmetic circuit;

a cache memory;

a second memory circuit configured to hold second data stored in the cache memory;

a first power supply control switch configured to control whether a power supply voltage is supplied to the arithmetic circuit or not;

a second power supply control switch configured to control whether a power supply voltage is supplied to the cache memory or not;

a first temperature detection circuit configured to detect a first temperature of the first memory circuit, to estimate an amount of a first extra power consumed at a time of writing the first data to the first memory circuit and a time of reading the first data from the first memory circuit from the first temperature; and

a second temperature detection circuit configured to detect a second temperature of the second memory circuit and to estimate an amount of a second extra power consumed at a time of writing the second data to the second memory circuit and a time of reading the second data from the second memory circuit from the second temperature,

wherein the first power supply control switch is configured to be turned off so as not to supply the power supply voltage to the arithmetic circuit during a first period, when a power consumption of the arithmetic circuit during the first period is larger than the first extra power, and configured to turn the second power supply control switch off so as not to supply the power supply voltage to the cache memory during a second period, when a power consumption of the cache memory during the second period is larger than the second extra power.

10. The semiconductor device according to claim 9, wherein the first memory circuit or the second memory circuit comprises a transistor in which a channel formation region comprises an oxide semiconductor.

11. The semiconductor device according to claim 9, wherein the first power supply control switch or the second power supply control switch comprises a transistor in which a channel formation region comprises an oxide semiconductor.

12. The semiconductor device according to claim 9, wherein the supply of the power supply voltage to the arithmetic circuit is controlled by a first transistor in the first power supply control switch.

13. A driving method of a semiconductor device comprising:

obtaining data by an arithmetic circuit;

detecting a temperature of a memory circuit by a temperature detection circuit;

calculating an amount of an extra power required to stop supplying power corresponding to power at a time of writing the data to the memory circuit and a time of reading the data from the memory circuit by the temperature detection circuit from the temperature;

determining whether a power consumption of the arithmetic circuit during a period is larger than the extra power when a power supply voltage is provided to the arithmetic circuit but processing is not performed in the arithmetic circuit during the period;

writing the data to the memory circuit before turning a power supply control switch off;

turning the power supply control switch off so as not to supply the power supply voltage to the arithmetic circuit;

turning the power supply control switch on so as to supply the power supply voltage to the arithmetic circuit if restoring of the data to the arithmetic circuit is needed; and

reading out the data from the memory circuit and restoring the data to the arithmetic circuit.