Techniques for reducing disturbance in a semiconductor memory device

• US 9,812,179 B2
• Filed: 06/24/2014
• Issued: 11/07/2017
• Est. Priority Date: 11/24/2009
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Inventors: Kwon, Jungtae, Kim, David, Bhardwaj, Sunil
• Primary Examiner(s): Huang, Min
• Application Number:
  US14/313,654
• Publication Number:
  US 20140307512A1
• Time in Patent Office: 1,232 Days
• Field of Search: 36518525
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

Techniques for reducing disturbance in a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device having reduced disturbance. The semiconductor memory device may comprise a plurality of memory cells arranged in arrays of rows and columns. The semiconductor memory device may also comprise a plurality of data sense amplifiers, coupled to the plurality of memory cells, configured to perform one or more operations during an operation/access cycle, wherein the operation/access cycle may comprise an operation segment and a disturbance recovery segment.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cells; and

data write and sense circuitry coupled to the plurality of memory cells, wherein the data write and sense circuitry comprises a plurality of local data sense amplifiers and a plurality of global data sense amplifiers, wherein the plurality of local data sense amplifiers are coupled to the plurality of memory cells via a plurality of local bit lines, wherein the plurality of global data sense amplifiers are coupled to the plurality of local data sense amplifiers via a plurality of global bit lines, wherein a first local data sense amplifier of the plurality of local data sense amplifiers is configured to determine a data state stored in a first memory cell of the plurality of memory cells during a first read operation, wherein a second local data sense amplifier of the plurality of local data sense amplifiers is configured to determine a data state stored in a second memory cell of the plurality of memory cells during a disturbance recovery operation after the first read operation, and wherein the disturbance recovery operation comprises a second read operation and a second writeback operation performed on the second memory cell before a first writeback operation is performed on the first memory cell.

2. The semiconductor memory device according to claim 1, wherein the data write and sense circuitry is configured to perform the first read operation and the first writeback operation on the first memory cell of the plurality of memory cells.

3. The semiconductor memory device according to claim 2, wherein the data write and sense circuitry is further configured to perform the disturbance recovery operation on the second memory cell of the plurality of memory cells.

4. The semiconductor memory device according to claim 1, wherein the plurality of local data sense amplifiers are arranged in one or more local data sense amplifier subarrays, and the plurality of global data sense amplifiers are arranged in one or more global data sense amplifier subarrays.

5. The semiconductor memory device according to claim 1, wherein a single global bit line couples at least a subset of the plurality of local data sense amplifiers to a single global data sense amplifier.

6. The semiconductor memory device according to claim 1, wherein the first local data sense amplifier is further configured to transfer the data state determined to be stored in the first memory cell to a first global data sense amplifier of the plurality of global data sense amplifiers.

7. The semiconductor memory device according to claim 6, wherein the second local data sense amplifier is further configured to write the data state determined to be stored in the second memory cell back to the second memory cell during the disturbance recovery operation.

8. The semiconductor memory device according to claim 7, wherein the first global data sense amplifier is configured to transfer the data state transferred to the first global data sense amplifier back to the first local data sense amplifier during a writeback operation.

9. The semiconductor memory device according to claim 8, wherein the first local data sense amplifier and the second local data sense amplifier are disposed in a single bank of local data sense amplifiers.

10. The semiconductor memory device according to claim 1, further comprising memory cell selection and control circuitry configured to select memory cells of the plurality of memory cells for conducting reading and writing operations thereon.

11. The semiconductor memory device according to claim 10, wherein the memory cell selection and control circuitry comprises a refresh address counter configured to identify row address signals corresponding to memory cells of the plurality of memory cells to be refreshed.

12. The semiconductor memory device according to claim 11, wherein the memory cell selection and control circuitry further comprises a row address multiplexer configured to multiplex one or more signals from the refresh address counter and one or more external address signals to generate row address signals corresponding to memory cells of the plurality of memory cells to be refreshed.

13. The semiconductor memory device according to claim 12, wherein the memory cell selection and control circuitry further comprises a disturb recovery address counter configured to identify disturb recovery row address signals corresponding to memory cells of the plurality of memory cells to be refreshed.

14. The semiconductor memory device according to claim 13, wherein the memory cell selection and control circuitry further comprises a disturb recovery address multiplexer configured to multiplex one or more signals from the row address multiplexer and one or more signals from the disturb recovery address counter to generate disturb recovery refresh address signals corresponding to memory cells of the plurality of memory cells to be refreshed.

15. The semiconductor memory device according to claim 14, wherein the memory cell selection and control circuitry further comprises a row decoder configured to decode disturb recovery refresh address signals to generate decoded disturb recovery refresh address signals corresponding to memory cells of the plurality of memory cells to be refreshed.

16. The semiconductor memory device according to claim 15, wherein the decoded disturb recovery refresh address signals are provided to the plurality of memory cells on word lines, source lines, or a combination thereof.

17. The semiconductor memory device according to claim 1, wherein the data write and sense circuitry comprises data sense amplifier selection circuits configured to select one or more of the plurality of local data sense amplifiers during at least read operations on the plurality of memory cells.