Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
First Claim
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1. A semiconductor memory cell comprising:
- a silicon controlled rectifier device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said silicon controlled rectifier device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type.
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Abstract
Semiconductor memory is provided wherein a memory cell includes a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell. The cell further includes a nonvolatile memory comprising a resistance change element configured to store data stored in the floating body under any one of a plurality of predetermined conditions. A method of operating semiconductor memory to function as volatile memory, while having the ability to retain stored data when power is discontinued to the semiconductor memory is described.
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21 Claims
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1. A semiconductor memory cell comprising:
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a silicon controlled rectifier device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell; a nonvolatile memory comprising a resistance change element configured to store data stored in said silicon controlled rectifier device upon transfer thereto; a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor memory cell comprising:
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a substrate; a transistor comprising a source region, a first floating body region, a drain region, and a gate; a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region, wherein; one of said cathode region and said anode region comprises said substrate; a state of said memory cell is stored in said first floating body region, said first floating body region and said second floating body region are common, said silicon controlled rectifier device maintains a state of said memory cell, and said transistor is usable to access said memory cell; and a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer thereto. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A semiconductor memory cell comprising:
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a silicon controlled rectifier device configured to store data when power is applied to said cell; and a nonvolatile memory comprising a resistance change element configured to store data stored in said silicon controlled rectifier device upon transfer thereto under any one of a plurality of predetermined conditions; wherein one of said predetermined conditions comprises loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said silicon controlled rectifier device is loaded into and stored in said nonvolatile memory; wherein, upon restoration of power to said cell, said data in said nonvolatile is loaded into said silicon controlled rectifier device and stored therein; and wherein said cell is configured to reset said nonvolatile memory to an initial state after loading said data into said silicon controlled rectifier device upon said restoration of power. - View Dependent Claims (18, 19, 20, 21)
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Specification