Flash memory, flash memory system and operating method of the same

• US 9,812,213 B2
• Filed: 04/14/2016
• Issued: 11/07/2017
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kyung-Ryun, Yoon, Sang-Yong
• Primary Examiner(s): Norman, James G
• Application Number:
  US15/098,791
• Publication Number:
  US 20160225458A1
• Time in Patent Office: 572 Days
• Field of Search: 36518503
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells

Abstract

A flash memory, a flash memory system, and an operating method thereof. The method of operating a flash memory includes counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range (defined by a first reference read voltage for distinguishing between initially separated adjacently located threshold voltage distributions and a first search read voltage having a first voltage difference from the first reference read voltage), and a second adjacent threshold voltage range (defined by the first reference read voltage and a second search read voltage having a second voltage difference from the first reference read voltage), and setting a first optimal read voltage based on the difference between the first and second counted numbers of the memory cells.

Claims

1. A method of operating a flash memory comprising a plurality of memory cells, the method comprising:

defining a first adjacent threshold voltage range and a second adjacent threshold voltage range for a first pair of threshold voltage distributions adjacently located;

counting the number of memory cells having threshold voltages included in the first adjacent threshold voltage range by subtracting the number of the memory cells having a threshold voltage lower than a first search read voltage from a number of the memory cells having a threshold voltage lower than a first reference read voltage;

counting the number of memory cells included in the second adjacent threshold voltage range by subtracting the number of the memory cells having a threshold voltage lower than the first reference read voltage from the number of the memory cells having a threshold voltage lower than a second search read voltage; and

setting a first optimal read voltage based on a count difference between the counted number of the memory cells having the threshold voltages included in the first adjacent threshold voltage range and the counted number of the memory cells having the threshold voltages included in the second adjacent threshold voltage range,

wherein setting the first optimal read voltage based on the count difference, is performed by calculating using a result value generated from applying a first adjustment parameter to the count difference, wherein the first adjustment parameter is a slope of a tangent at the origin of a graph representing the count difference verses a threshold voltage of the memory cells.

2. The method of claim 1, wherein the first adjacent threshold voltage range is defined by the first reference read voltage for discriminating between the first pair of threshold voltage distributions adjacently located and the first search read voltage having a first voltage difference with the first reference read voltage, and the second adjacent threshold voltage range is defined by the first reference read voltage and the second search read voltage having a second voltage difference with the first reference read voltage.

3. The method of claim 2, wherein the first optimal read voltage has a voltage level that is shifted from the first reference read voltage by the result value.

4. The method of claim 2, wherein the first pair of the threshold voltage distributions has the form of a Gaussian distribution, and the first adjustment parameter is independent of the standard deviation of the adjacently located threshold voltage distribution.

5. The method of claim 2, further comprising:

counting the number of memory cells having threshold voltages included in a third threshold voltage range defined by the second reference read voltage for discriminating between a second pair of threshold voltage distributions adjacently located and a third search read voltage having a third voltage difference from the second reference read voltage, and

counting the number of memory cells having threshold voltages included in a fourth threshold voltage range defined by the second reference read voltage and a fourth search read voltages having a fourth voltage difference from the second reference read voltage; and

setting a second optimal read voltage based on a result value generated by applying a second adjustment parameter to a count difference between the number of memory cells having threshold voltages included in the third threshold voltage range and the number of memory cells having threshold voltages included in the fourth threshold voltage range.

6. The method of claim 5, wherein the first adjustment parameter and the one second adjustment parameter are the same.

7. The method of claim 5, wherein the first adjustment parameter is different from the second adjustment parameter.

8. The method of claim 2, further comprises setting the first reference read voltage based on initial states of the first pair of the threshold voltage distributions before the counting the number of memory cells having threshold voltages included in the first adjacent threshold voltage range and the number of memory cells having threshold voltages included in the second adjacent threshold voltage range.

9. The method of claim 2, wherein the first search read voltage and the second search read voltage are a pair of soft read voltages for the first pair of the threshold voltage distributions.

10. The method of claim 1, wherein the first pair of the threshold voltage distributions include two different program states.

11. The method of claim 1, wherein the first pair of the threshold voltage distributions include an erasing state and a first program state.

12. The method of claim 1, wherein the first pair of the threshold voltage distributions include the program state having a highest threshold voltage among threshold voltage distributions which are set for the flash memory.

13. The method of claim 1, wherein the memory cells are arranged vertically from a substrate.

14. A method of operating a flash memory comprising a plurality of memory cells, comprising:

respectively counting the number of memory cells having threshold voltages included in a first adjacent threshold voltage range and a second adjacent voltage range defined by a first reference read voltage and a pair of first search read voltages having a first voltage difference and a second voltage difference from the first reference read voltage, respectively; and

setting a first optimal read voltage based on a result value generated by applying an first adjustment parameter to the difference between the number of memory cells having threshold voltages within the first adjacent threshold voltage range and the number of memory cells having threshold voltages within the second adjacent threshold voltage range,

wherein the memory cells are multi-level cells arranged vertically from a substrate,

wherein the first adjustment parameter is a slope of a tangent at the origin of a graph representing the difference verses a threshold voltage of the memory cells.

15. A memory device comprising:

a memory cell array including a plurality of memory cells; and

an on-chip controller configured to set a first optimal read voltage for the memory cell array in response to an external control signal, the on-chip controller comprising;

a counter configured to count the number of memory cells included, respectively, in a first adjacent threshold voltage range and a second adjacent threshold voltage range, defined by a first reference read voltage and by a pair of first search read voltages respectively having a first voltage difference and a second voltage difference from the first reference read voltage; and

a control logic configured to set the first optimal read voltage based on a result value generated by applying a first adjustment parameter to a difference between the number of memory cells having threshold voltages included within the first adjacent threshold voltage range and the number of memory cells having threshold voltages included within the second adjacent threshold voltage range,

wherein the first adjustment parameter is a slope of a tangent at the origin of a graph representing the difference verses a threshold voltage of the memory cells.

16. The memory device of claim 15, wherein the memory cell array comprises a plurality of strings, each string comprising the plurality of memory cells stacked in a vertical direction to a substrate.

17. The memory device of claim 15, wherein the first adjustment parameter is a constant regarding the difference between the number of memory cells having the threshold voltages included in the first adjacent threshold voltage range and the second adjacent threshold voltage range, and is independent of the standard deviation of the first and second threshold voltage distributions which includes the first adjacent threshold voltage range and the second adjacent threshold voltage range and are formed as Gaussian distributions.

18. The memory device of claim 15, wherein the first optimal read voltage has a voltage level that is shifted from the first reference read voltage by the result value.

19. The memory device of claim 15, wherein the first adjustment parameter is set differently according to the counted number of erasures of the memory cells having the threshold voltages within the first pair of the threshold voltage distributions.