Buffered multi-rank memory modules configured to selectively link rank control signals and methods of operating the same

• US 9,812,220 B2
• Filed: 07/12/2016
• Issued: 11/07/2017
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Tae-Hyung, Shin, Huichong, Kim, Seokil, Yun, Young, Lim, Jonghyoung, Han, Youkeun
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US15/207,557
• Publication Number:
  US 20170092379A1
• Time in Patent Office: 483 Days
• Field of Search: 365189011-18912
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits

Abstract

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

Claims

1. A memory module, comprising:

a plurality of semiconductor memory devices on a substrate to provide a dual in-line memory module (DIMM) organized into at least two ranks; and

a memory buffer,

wherein when a parallel bit test operation is started with respect to the plurality of semiconductor memory devices, the memory buffer changes a rank control signal received from a memory controller from inactive to active based on a mapping table defined according to a mode register set signal to perform the parallel bit test operation simultaneously to all the ranks.

2. The memory module of claim 1, wherein the plurality of semiconductor memory devices provide the DIMM a dual rank or quad rank structure.

3. The memory module of claim 1, wherein each of the semiconductor memory devices is a double data rate (DDR) DRAM.

4. The memory module of claim 1, wherein the memory module is configured as have a registered DIMM (RDIMM) structure or load reduced DIMM (LDIMM) structure.

5. The memory module of claim 1, wherein the memory buffer changes a state of a clock enable signal into an active state or inactive state for each rank based on the mapping table when the clock enable signal is transmitted from the memory controller for each rank.

6. The memory module of claim 1, wherein the memory buffer is configured to change a state of an on-die termination signal to active or inactive for each rank when the on-die termination signal is transmitted from the memory controller for each rank based on the mapping table.

7. The memory module of claim 1, wherein the memory buffer bypasses an active rank control signal related to a selected rank based on the mapping table.

8. The memory module of claim 1, wherein the memory module is connected to the memory controller to provide a high bandwidth memory system.

9. The memory module of claim 1, wherein the memory buffer comprises:

an input buffer configured to determine whether to output the rank control signal when inactive or to ignore the rank control signal when inactive; and

a switching unit selectively fixing an output of the input buffer to a high state or a low state.

10. The memory module of claim 1, wherein a parallel bit test operation of the memory module is performed during a power-up sequence of the memory module.