Wire bond wires for interference shielding

• US 9,812,402 B2
• Filed: 11/07/2016
• Issued: 11/07/2017
• Est. Priority Date: 10/12/2015
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Awujoola, Abiola, Sun, Zhuowen, Zohni, Wael, Prabhu, Ashok S., Subido, Willmar
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US15/344,990
• Publication Number:
  US 20170117231A1
• Time in Patent Office: 365 Days
• Field of Search: 257659, 257686, 257777
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/215 Material
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48105 Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48472 : the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4942 : Ball bonds
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73227 : Wire and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85455 : Nickel (Ni) as principal constituent
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1052 : Wire or wire-like electrical connections
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/1206 : Inductor
• CPC Class Codes: H01L 2924/1207 : Resistor
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/2075 : larger or equal to 1 micron less than 10 microns
• CPC Class Codes: H01L 2924/20751 : larger or equal to 10 microns less than 20 microns
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/20754 : larger or equal to 40 microns less than 50 microns
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Apparatuses relating generally to a microelectronic package having protection from interference are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface and has a ground plane. A first microelectronic device is coupled to the upper surface of the substrate. Wire bond wires are coupled to the ground plane for conducting the interference thereto and extending away from the upper surface of the substrate. A first portion of the wire bond wires is positioned to provide a shielding region for the first microelectronic device with respect to the interference. A second portion of the wire bond wires is not positioned to provide the shielding region. A second microelectronic device is coupled to the substrate and located outside of the shielding region. A conductive surface is over the first portion of the wire bond wires for covering the shielding region.

Claims

1. An apparatus for a microelectronic package having protection from interference, comprising:

a substrate having an upper surface and a lower surface opposite the upper surface and having a ground plane;

a microelectronic device coupled to the upper surface of the substrate;

wire bond wires having lower ends coupled to the ground plane, the wire bond wires extending away from the upper surface of the substrate;

the wire bond wires positioned to surround the microelectronic device to provide a shielding region for the microelectronic device with respect to the interference;

a conductive surface positioned above the wire bond wires for covering the shielding region; and

the wire bond wires having upper ends coupled to the conductive surface.

2. The apparatus according to claim 1, wherein the conductive surface is positioned over the upper ends of the wire bond wires, and wherein the upper ends are mechanically coupled to an underside of the conductive surface.

3. The apparatus according to claim 2, further comprising:

a second microelectronic device coupled to the substrate and located outside of the shielding region;

wherein the substrate is a package substrate of a system-in-package device.

4. The apparatus according to claim 2, wherein the microelectronic device includes a passive component.

5. The apparatus according to claim 4, wherein the passive component is selected from a group consisting of a capacitor, an inductor, and a resistor.

6. The apparatus according to claim 1, wherein an interconnected combination of the ground plane, the conductive surface, and the wire bond wires provides a Faraday cage.

7. The apparatus according to claim 1, wherein the upper ends are a first portion of the upper ends of the wire bond wires;

and wherein a second portion of the upper ends of the wire bond wires extend through holes in the conductive surface.

8. The apparatus according to claim 1, further comprising:

bond pads positioned proximate to and around the microelectronic device on the upper surface of the substrate for respectively coupling the lower ends of the wire bond wires thereto for the shielding region; and

the bond pads having a pad-to-pad pitch equal to or less than approximately 250 microns.

9. The apparatus according to claim 1, wherein the substrate and the ground plane respectively are a first substrate and a first ground plane, the apparatus further comprising:

a second substrate having a second ground plane;

upper ends of the wire bond wires coupled to a bottom surface of the second substrate for coupling to the second ground plane; and

a second microelectronic device coupled to a top surface of the second substrate.

10. An apparatus for a microelectronic package having protection from interference, comprising:

a substrate having an upper surface and a lower surface opposite the upper surface and having a ground plane;

a microelectronic device coupled to the upper surface of the substrate;

wire bond wires bonded to and extending away from the upper surface of the substrate;

the wire bond wires positioned proximate to and around the microelectronic device for providing a shielding region for the microelectronic device with respect to the interference, the wire bond wires coupled to the ground plane for conducting the interference thereto;

a conductive surface over the wire bond wires for covering the shielding region; and

upper ends of the wire bond wires mechanically coupled to the conductive surface and extending above a top surface of the microelectronic device.

11. The apparatus according to claim 10, wherein the microelectronic device is a first microelectronic device, the apparatus further comprising a second microelectronic device coupled to the substrate and located outside of the shielding region.

12. The apparatus according to claim 10, further comprising:

bond pads positioned proximate to and around the microelectronic device on the upper surface of the substrate for bonding the wire bond wires to the upper surface of the substrate; and

the bond pads having a pad-to-pad pitch equal to or less than approximately 250 microns.

13. The apparatus according to claim 10, wherein the substrate, the ground plane and the microelectronic device respectively are a first substrate, a first ground plane and a first microelectronic device, the apparatus further comprising:

a second substrate located over the first microelectronic device and having a second ground plane as the conductive surface, the second substrate located over the upper ends of the wire bond wires; and

a second microelectronic device coupled to a top surface of the second substrate.

14. The apparatus according to claim 10, wherein an interconnected combination of the ground plane, the conductive surface, and the wire bond wires provides a Faraday cage.

15. An apparatus for a microelectronic package having protection from interference, comprising:

a substrate having an upper surface and a lower surface opposite the upper surface and having a ground plane;

a first microelectronic device coupled to the upper surface of the substrate;

lower ends of wire bond wires coupled to the ground plane for conducting the interference thereto;

the wire bond wires extending away from the upper surface of the substrate;

the wire bond wires positioned to provide a shielding region for the first microelectronic device with respect to the interference;

a second microelectronic device coupled to the substrate and located outside of the shielding region; and

a conductive surface having upper ends of the wire bond wires coupled thereto, the conductive surface covering the shielding region.

16. The apparatus according to claim 15, further comprising:

bond pads positioned proximate to and around the first microelectronic device on the upper surface of the substrate for coupling the lower ends of the wire bond wires thereto for providing the shielding region for the microelectronic device with respect to the interference; and

the bond pads having a pad-to-pad pitch equal to or less than approximately 250 microns.

17. The apparatus according to claim 15, wherein an interconnected combination of the ground plane, the conductive surface, and the wire bond wires provides a Faraday cage.

18. The apparatus according to claim 15, wherein the substrate and the ground plane respectively are a first substrate and a first ground plane, the apparatus further comprising:

a second substrate having a second ground plane;

the wire bond wires coupled to a bottom surface of the second substrate for coupling to the second ground plane as the conductive surface; and

a third microelectronic device coupled to a top surface of the second substrate.

19. The apparatus according to claim 15, wherein the first microelectronic device includes an integrated circuit die.

20. The apparatus according to claim 15, wherein the first microelectronic device includes a passive component.