Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor
First Claim
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1. A multi-port semiconductor memory cell comprising:
- a plurality of gates;
a common body region insulated from said plurality of gates and of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and
a plurality of conductive regions of a second conductivity type,wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;
wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and
wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.
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Abstract
Multi-port semiconductor memory cells including a common floating body region configured to be charged to a level indicative of a memory state of the memory cell. The multi-port semiconductor memory cells include a plurality of gates and conductive regions interfacing with said floating body region. Arrays of memory cells and method of operating said memory arrays are disclosed for making a memory device.
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Citations
20 Claims
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1. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region insulated from said plurality of gates and of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and a plurality of conductive regions of a second conductivity type, wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions; wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A semiconductor memory cell comprising:
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a substrate region; a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said semiconductor memory cell; a plurality of conductive regions of a second conductivity type, wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions; and an insulator layer located beneath said common body region insulating said common body region from the substrate; wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A multi-port semiconductor memory cell comprising:
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a plurality of gates; a common body region of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and a plurality of conductive regions of a second conductivity type, wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions; wherein said multi-port semiconductor memory cell is configured to assume at least two stable common body region charge levels. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification