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Dual-port semiconductor memory and first in first out (FIFO) memory having electrically floating body transistor

  • US 9,812,456 B2
  • Filed: 01/24/2017
  • Issued: 11/07/2017
  • Est. Priority Date: 11/16/2010
  • Status: Active Grant
First Claim
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1. A multi-port semiconductor memory cell comprising:

  • a plurality of gates;

    a common body region insulated from said plurality of gates and of a first conductivity type configured to store a charge that is indicative of a memory state of said multi-port semiconductor memory cell; and

    a plurality of conductive regions of a second conductivity type,wherein adjacent ones of each of said plurality of gates are separated by a respective one of the plurality of conductive regions, and wherein the common body region extends continuously beneath at least one of the plurality of conductive regions;

    wherein one of said plurality of conductive regions of a second conductivity type is electrically connected to a back bias terminal; and

    wherein applying a voltage to said back bias terminal results in at least two stable common body region charge levels.

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