Semiconductor device and method for manufacturing the same

• US 9,812,537 B2
• Filed: 02/14/2014
• Issued: 11/07/2017
• Est. Priority Date: 02/19/2013
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki
• Primary Examiner(s): Sarkar, Asok K
• Assistant Examiner(s): Yemelyanov, Dmitriy
• Application Number:
  US14/768,116
• Publication Number:
  US 20150380503A1
• Time in Patent Office: 1,362 Days
• Field of Search: 257 77, 257 76, 438270
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device of the present invention includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type formed with a gate trench;

a gate electrode buried in the gate trench via a gate insulating film;

a source region of a first conductivity type disposed in a manner exposed on a surface of the semiconductor layer, forming a part of a side face of the gate trench;

a channel region of a second conductivity type disposed for the source region on a back surface side of the semiconductor layer in a manner contacting the source region, forming a part of the side face of the gate trench;

a drain region of a first conductivity type disposed for the channel region on the back surface side of the semiconductor layer in a manner contacting the channel region, forming a bottom face of the gate trench;

a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer;

a trench buried portion buried in the second trench;

a channel contact region of a second conductivity type selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, electrically connected with the channel region;

a surface metal layer disposed on the source portion, electrically connected to the source region and the channel contact region; and

a second conductivity-type layer formed at the bottom portion and a side portion of the second trench in a manner continuing from the channel region and the channel contact region.

2. The semiconductor device according to claim 1, wherein the trench buried portion consists of an insulating film formed on an inner surface of the second trench and a polysilicon layer buried inside of the insulating film.

3. The semiconductor device according to claim 2, wherein the insulating film is made of any of SiO₂, AlON, Al₂O₃, SiO₂/AlON, SiO₂/AlON/SiO₂, SiO₂/SiN, and SiO₂/SiN/SiO₂.

4. The semiconductor device according to claim 2, wherein the insulating film has a SiO₂ film containing nitrogen (N).

5. The semiconductor device according to claim 2, wherein the insulating film is, at the bottom portion of the second trench, formed to be thicker than a part at a side portion of the second trench.

6. The semiconductor device according to claim 2, wherein the polysilicon layer is made of n⁺-type polysilicon.

7. The semiconductor device according to claim 1, wherein the trench buried portion consists of an insulating layer that fills back the second trench.

8. The semiconductor device according to claim 7, wherein the insulating layer is made of SiO₂.

9. The semiconductor device according to claim 8, wherein the insulating layer is made of SiO₂ containing phosphorus (P) or boron (B).

10. The semiconductor device according to claim 1, wherein the trench buried portion consists of a polysilicon layer that fills back the second trench.

11. The semiconductor device according to claim 10, wherein the polysilicon layer is made of p⁺-type polysilicon.

12. The semiconductor device according to claim 1, wherein the gate electrode is a metal gate electrode containing any of Mo, W, Al, Pt, Ni, and Ti.

13. The semiconductor device according to claim 1, wherein the surface metal layer is made of a metal containing copper (Cu).

14. The semiconductor device according to claim 13, wherein the surface metal layer includes an Al—

Cu-based alloy.

15. The semiconductor device according to claim 1, wherein the second trench has an annular structure surrounding the channel contact region.

16. The semiconductor device according to claim 1, wherein the second trench has a width the same as that of the gate trench.

17. The semiconductor device according to claim 1, wherein the semiconductor layer has an active region that forms a channel in the channel region to perform a transistor operation and an outer peripheral region disposed around the active region, and

the semiconductor device further comprises a surface insulating film disposed in a manner extending across the active region and the outer peripheral region, and in the active region, formed to be thinner than a part in the outer peripheral region.

18. The semiconductor device according to claim 17, wherein the surface insulating film has a thickness of 5000 Å

or less in the active region.

19. The semiconductor device according to claim 17, wherein in the surface insulating film, a contact hole that selectively exposes the source portion is formed over the entire surface of the semiconductor layer.

20. The semiconductor device according to claim 1, wherein in the semiconductor layer, a unit cell that forms a channel in the channel region to perform a transistor operation are defined in a grid shape by the gate trench.

21. The semiconductor device according to claim 1, wherein in the semiconductor layer, a unit cell that forms a channel in the channel region to perform a transistor operation are defined in a striped shape by the gate trench.

22. The semiconductor device according to claim 1, wherein the semiconductor layer is made of SiC, GaN, or diamond.

23. A method for manufacturing a semiconductor device comprising:

a step of simultaneously forming, in a semiconductor layer formed with a source region of a first conductivity type, a channel region of a second conductivity type, and a drain region of a first conductivity type in order from a surface side to a back surface side in a manner contacting each other, a gate trench and a second trench that penetrate through the source region and the channel region from the surface to reach the drain region;

a step of selectively forming a channel contact region of a second conductivity type to be electrically connected with the channel region, at a position higher than that of a bottom portion of the second trench in the semiconductor layer;

a step of burying a gate electrode via a gate insulating film in the gate trench;

a step of burying a trench buried portion in the second trench;

a step of selectively exposing a source portion containing the source region, the channel contact region, and the trench buried portion in the surface of the semiconductor layer, and

selectively covering a part other than the source portion;

a step of forming, on the source portion, a surface metal layer to be electrically connected to the source region and the channel contact region; and

a step of forming a second conductivity-type layer at the bottom portion and a side portion of the second trench in a manner continuing from the channel region and the channel contact region.

24. The method for manufacturing a semiconductor device according to claim 23, wherein the step of burying the trench buried portion includes a step of forming an insulating film on an inner surface of the second trench and then burying a polysilicon layer inside of the insulating film.

25. The method for manufacturing a semiconductor device according to claim 23, wherein the step of burying the trench buried portion includes a step of filling back the second trench with an insulating layer.

26. The method for manufacturing a semiconductor device according to claim 23, wherein the step of burying the trench buried portion includes a step of filling back the second trench with a polysilicon layer.

27. The method for manufacturing a semiconductor device according to claim 23, wherein the step of forming the gate trench and the second trench includes a step of forming a gate trench and a second trench being the same width as each other.