Semiconductor structure with multiple transistors having various threshold voltages

• US 9,812,550 B2
• Filed: 01/30/2017
• Issued: 11/07/2017
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Zhao, Dalong, Bakhishev, Teymur, Scudder, Lance, Gregory, Paul E., Duane, Michael, Sridharan, U. C., Ranade, Pushkar, Shifren, Lucian, Hoffmann, Thomas
• Primary Examiner(s): Fan, Bo
• Application Number:
  US15/419,315
• Publication Number:
  US 20170141209A1
• Time in Patent Office: 281 Days
• Field of Search: 257345, 438 33, 438 46, 438 93, 438406, 438107, 438478, 438276
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Claims

1. A method of fabricating a semiconductor structure, comprising:

implanting in a substrate a first antipunchthrough region with a first doping concentration;

implanting in the substrate a second antipunchthrough region with a second doping concentration;

implanting in the substrate a screening region with a third doping concentration;

forming a substantially undoped channel on the substrate;

forming a gate on the substrate;

implanting in the substrate a source and a drain;

wherein the screening region is located to be below a surface of the substrate at a distance of at least less than 1.5 times a length of the gate and above a bottom of the source and drain to which the screening region abuts;

wherein the first antipunchthrough region underlies the screening region and the first doping concentration is less than the third doping concentration;

wherein the second antipunchthrough region underlies the first antipunchthrough region and the second doping concentration is less than the third doping concentration.