Voltage regulator with improved overshoot and undershoot voltage compensation

• US 9,812,958 B2
• Filed: 03/04/2014
• Issued: 11/07/2017
• Est. Priority Date: 03/06/2013
• Status: Active Grant

• Current Assignee: Ablic Inc. (Minebea Mitsumi, Inc.)
• Original Assignee: SII Semiconductor Corporation (MinebeaMitsumi Inc.)
• Inventors: Utsunomiya, Fumiyasu
• Primary Examiner(s): Gblende, Jeffrey
• Assistant Examiner(s): Singh, David A
• Application Number:
  US14/196,723
• Publication Number:
  US 20140253076A1
• Time in Patent Office: 1,344 Days
• Field of Search: 323312-316, 323273, 323276-278, 323282-284, 327539-541, 327100, 327306, 327331-332, 363 55, 363 5601- 5605
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

A voltage regulator includes an error amplifier; an output transistor; and a first transistor including a gate for inputting a reference voltage and a source for inputting an output voltage. The first transistor is configured to cause a current to flow when the output voltage becomes an irregular voltage, and a current of the output transistor is controlled based on the current flowing through the first transistor. The voltage regulator capable of improving the overshoot or undershoot of the output voltage in a wide temperature range and to reduce a delay in detection of the overshoot or undershoot.

Claims

1. A voltage regulator, comprising:

an error amplifier having an error output node having a voltage proportional to a difference between an inverting input and a non-inverting input of the error amplifier that is coupled to a first voltage reference;

an I-V converter circuit that comprises a first transistor having a gate coupled to the error output node of the error amplifier, and a second transistor having a gate and drain coupled to a drain of the first transistor and a drive output node;

an output transistor having a gate terminal coupled to the drive output node of the I-V converter circuit and an output terminal configured to output a voltage of the voltage regulator for driving a load, wherein the error output node and the drive output node are different; and

a third transistor that includes a gate configured to receive a second reference voltage from a reference voltage generator circuit that is separate from the I-V converter circuit, a source coupled to the output terminal, and a drain that is connected to an internal node of the I-V converter circuit,

wherein when the output voltage deviates from the second reference voltage by more than a predetermined threshold, current flows directly between the third transistor and the internal node of the I-V converter circuit to thereby control a current of the output transistor,

wherein the value of the second reference voltage received at the gate of the third transistor is set to be less than, equal to, or greater than the first voltage reference.

2. A voltage regulator according to claim 1, wherein the I-V converter circuit is configured to control the current flowing through the output transistor based on a current controlled by the voltage present on the error output node of the error amplifier and the current flowing through the third transistor.

3. The voltage regulator according to claim 2, wherein the I-V converter circuit comprises a cascode transistor provided between the first transistor and the second transistor.

4. The voltage regulator according to claim 1, wherein the I-V converter circuit comprises a cascode transistor provided between the first transistor and the second transistor.