Digital processor having instruction set with complex angle function

• US 9,813,224 B2
• Filed: 04/17/2014
• Issued: 11/07/2017
• Est. Priority Date: 04/17/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Azadet, Kameran
• Primary Examiner(s): Giroux, George
• Application Number:
  US14/255,491
• Publication Number:
  US 20140317376A1
• Time in Patent Office: 1,300 Days
• Field of Search: None
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver
• CPC Class Codes: H04B 1/62 for providing a predistortion of the signal in the transmitter and corresponding correction in the receiver, e.g. for improving the signal/noise ratio
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion
• CPC Class Codes: H04B 7/0417 Feedback systems
• CPC Class Codes: H04J 11/004 using regenerative subtractive interference cancellation
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 25/03012 operating in the time domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 27/367 using predistortion
• CPC Class Codes: H04L 27/368 adaptive predistortion
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits

Abstract

A digital processor, such as a vector processor or a scalar processor, is provided having an instruction set with a complex angle function. A complex angle is evaluated for an input value, x, by obtaining one or more complex angle software instructions having the input value, x, as an input; in response to at least one of the complex angle software instructions, performing the following steps: invoking at least one complex angle functional unit that implements the one or more complex angle software instructions to apply the complex angle function to the input value, x; and generating an output corresponding to the complex angle of the input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of the digital processor, wherein the complex angle software instruction is part of an instruction set of the digital signal processor. Multiplication operations optionally employ one or more multipliers of the MAC unit of the digital processor.

Claims

1. A method performed by a digital processor for evaluating a complex angle for an input value, x, comprising:

obtaining one or more complex angle software instructions having said input value, x, as an input;

in response to at least one of said complex angle software instructions, performing the following steps;

invoking at least one complex angle functional unit that implements said one or more complex angle software instructions to apply said complex angle function to said input value, x; and

generating an output corresponding to said complex angle of said input value, x, using one or more multipliers of a Multiply accumulate (MAC) unit of said digital processor,

wherein said complex angle software instruction is part of an instruction set of said digital signal processor, and

wherein said complex angle instruction computes the phase of an input complex number by successive approximation, computing a rotated version initialized to the input complex number at a first iteration, and at iteration k rotating the rotated signal from a previous iteration to produce a new rotated input.

2. The method of claim 1, further comprising the step of producing a magnitude of the complex number as the real part of the rotated number from a previous iteration.

3. The method of claim 1, wherein said multiplication operations employ said one or more multipliers of said MAC unit of said digital processor.

4. The method of claim 1, wherein said digital processor executes software instructions from program code.

5. The method of claim 1, wherein said digital processor comprises one or more of a vector processor and a scalar processor.

6. The method of claim 5, wherein said vector processor computes the argument of multiple complex numbers simultaneously.

7. The method of claim 1, wherein said digital processor further comprises a polar conversion software instruction implemented using said at least one complex angle functional unit in conjunction with at least one magnitude functional unit.

8. The method of claim 1 wherein at iteration k the rotated signal is rotated by sign (k)*π

*2<

sup>

k<

/sup>

to produce a new rotated input, where sign (k) is opposite of the sign of the imaginary part of said rotated number at said previous iteration.

9. A digital processor that evaluates a complex angle function for an input value, x, the complex angle having a magnitude component and a phase angle component, comprising:

A memory; and

at least one hardware device, coupled to the memory, operative to;

obtain one or more complex angle software instructions having said input value, x, as an input and in response to at least one of said complex angle software instructions, performing the following;

invoke at least one complex angle functional unit that implements said one or more complex angle software instructions to apply said complex angle function to said input value, x; and

generate an output corresponding to said complex angle of said input value, x, using one or more multipliers of a Multiply Accumulate (MAC) unit of said digital processor, wherein said complex angle instruction computes the phase of an input complex number by successive approximation, computing a rotated version initialized to the input complex number at a first iteration, and at iteration k rotating said rotated signal from a previous iteration to produce a new rotated input.

10. The digital processor of claim 9, wherein said at least one hardware device is further configured to produce a magnitude of the complex number as the real part of the rotated number from a previous iteration.

11. The digital processor of claim 9, wherein said multiplication operations employ said one or more multipliers of said MAC unit of said digital processor.

12. The digital processor of claim 9, wherein said digital processor executes software instructions from program code.

13. The digital processor of claim 9, wherein said digital processor is embodied as one or more of a vector processor and a scalar processor.

14. The digital processor of claim 13, wherein said vector processor computes the argument of multiple complex numbers simultaneously.

15. The digital processor of claim 9, further comprising a polar conversion software instruction implemented using said at least one complex angle functional unit in conjunction with at least one magnitude functional unit.

16. The digital processor of claim 9 wherein at iteration k the rotated signal is rotated by sign (k)*π

*2<

sup>

k<

/sup>

to produce a new rotated input, where sign (k) is opposite of the sign of the imaginary part of said rotated number at said previous iteration.