Wiring board and method of manufacturing same

• US 9,814,137 B2
• Filed: 04/22/2016
• Issued: 11/07/2017
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Asai, Ryota
• Primary Examiner(s): Chen, Xiaoliang
• Application Number:
  US15/135,638
• Publication Number:
  US 20160242286A1
• Time in Patent Office: 564 Days
• Field of Search: 174251, 174258, 428209, 428210, 3613014, 361312, 3613214
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/038 Textiles used as reinforcing materials for organic insulating substrates H05K1/0366
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/0145 Polyester, e.g. polyethylene terephthalate [PET], polyethylene naphthalate [PEN]
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/0338 Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
• CPC Class Codes: H05K 2201/0391 Using different types of conductors
• CPC Class Codes: H05K 2201/099 Coating over pads, e.g. solder resist partly over pads
• CPC Class Codes: H05K 2201/09909 Special local insulating pattern, e.g. as dam around component
• CPC Class Codes: H05K 3/108 by semi-additive methods; masks therefor characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241
• CPC Class Codes: H05K 3/244 Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: H05K 3/28 Applying non-metallic protective coatings H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673

Abstract

A wiring board is provided with: an insulating layer; a base electrode layer layered on one primary surface of the insulating layer in predetermined regions; an insulating covering layer layered on one primary surface of the insulating layer in a state covering parts of edges of the base electrode layer; and a surface electrode layer plated on exposed portions of the base electrode layer not covered by the insulating covering layer, the thickness of covered portions of the base electrode layer covered by the insulating covering layer being less than the thickness of the exposed portions. The surface electrode layer is formed only on the exposed portions of the base electrode layer.

Claims

1. A wiring board comprising:

an insulating layer;

a base electrode layer layered upon a predetermined region of one primary surface of the insulating layer;

an insulating covering layer layered upon the one primary surface of the insulating layer in a state covering at least part of an edge portion of the base electrode layer; and

a surface electrode layer plated on an exposed portion of the base electrode layer that is not covered by the insulating covering layer,

wherein the covered portion of the base electrode layer covered by the insulating covering layer is formed so as to be thinner than the exposed portion,

wherein the covered portion of the base electrode layer has a pattern that is T-shaped when viewed in plan view; and

a leg portion of the T-shaped pattern is connected to an edge portion of the exposed portion.

2. The wiring board according to claim 1,

further comprising a plurality of the base electrode layers adjacent to each other,

wherein the insulating covering layer is formed so as to span a gap between the adjacent base electrode layers.

3. The wiring board according to claim 1,

wherein the insulating covering layer on the covered portion is no less than 1 μ

m thick.

4. The wiring board according to claim 1,

wherein the insulating covering layer on the covered portion is no less than 5 μ

m thick.

5. The wiring board according to claim 1, wherein a width of the T-shaped covered portion of the base electrode layer is less than ½

of a minimum width of the exposed portion.