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Processor power management responsive to a sequence of an instruction stream

  • US 9,817,470 B2
  • Filed: 02/24/2016
  • Issued: 11/14/2017
  • Est. Priority Date: 02/25/2015
  • Status: Active Grant
First Claim
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1. An apparatus, comprising:

  • a first circuit;

    a second circuit, wherein the first circuit and the second circuit share an instruction stream; and

    a voltage controller circuit configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream and a performance mode, wherein one of the at least one low-power voltage comprises a power off mode and the voltage controller circuit is further configured to stall an instruction pipeline of the first circuit, exit the power off mode, and unstall the instruction pipeline based on the performance mode.

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