Systems and methods for generating optimized hardware descriptions for models

• US 9,817,931 B1
• Filed: 12/05/2014
• Issued: 11/14/2017
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: The MathWorks, Inc.
• Original Assignee: The MathWorks, Inc.
• Inventors: Gu, Yongfeng, Venkataramani, Girish, Kokku, Rama
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/562,382
• Time in Patent Office: 1,075 Days
• Field of Search: 716103, 716106, 716111, 716132, 716133, 703 16
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 8/35 model driven

Abstract

Systems and methods automatically generate optimized hardware description language (HDL) code for an executable model. An intermediate representation is generated for the executable model, which includes model elements. The intermediate representation includes nodes corresponding to the model elements. The HDL code is generated from the intermediate representation. A synthesis tool chain performs hardware synthesis using the HDL code. The synthesis tool chain generates performance characteristics of hardware components defined by the synthesis tool chain. The performance characteristics are mapped to the nodes of the intermediate representation, and one or more performance bottlenecks are identified. At least one optimization technique is applied to the intermediate representation to produce a revised intermediate representation, which is then used to generate new HDL code. The process may be repeated until the performance bottlenecks are eliminated or a termination criterion is met.

Claims

1. A method comprising:

storing in a memory a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model;

automatically generating, by a processor configured to access the first intermediate representation from the memory, hardware description language (HDL) code from the first intermediate representation;

receiving one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code;

mapping the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation;

selecting, by the processor, an optimization technique;

applying the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption;

repeating the automatically generating, the receiving, the mapping, the selecting, and the applying steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code; and

configuring a programmable hardware element based on the HDL code or the revised HDL code.

2. The method of claim 1 further comprising:

generating a genealogy graph configured to provide a temporal representation of the plurality of nodes included in the first intermediate representation and intermediate representation nodes in the revised intermediate representation.

3. The method of claim 2, wherein the mapping includes:

utilizing the genealogy graph to back annotate the first intermediate representation or the revised intermediate representation with the one or more hardware performance characteristics.

4. The method of claim 1 further comprising:

mapping the one or more hardware performance characteristics received from the hardware synthesis tool to portions of the HDL code or the revised HDL code; and

tracing the one or more hardware performance characteristics, as mapped to the portions of the HDL code or the revised HDL code, back to the first intermediate representation or to the revised intermediate representation.

5. The method of claim 4, wherein the HDL code or the revised HDL code includes function names and variable names, the method further comprising:

at least one of prepending or appending predetermined delimiters to the function names and to the variable names; and

locating occurrences of the predetermined delimiters in the one or more hardware performance characteristics, where

the mapping of the one or more hardware performance characteristics to the portions of the HDL code or the revised HDL code is based on the occurrences of the predetermined delimiters located in the one or more hardware performance characteristics.

6. The method of claim 1, wherein the one or more hardware performance characteristics are included in a hardware synthesis report produced by the hardware synthesis tool, the method further comprising:

utilizing a communication interface coupled to the hardware synthesis tool to obtain at least a portion of the hardware synthesis report.

7. The method of claim 6, wherein the communication interface includes an Application Programming Interface (API) of the hardware synthesis tool.

8. The method of claim 1, wherein the one or more hardware performance characteristics are included in design objects constructed by the hardware synthesis tool.

9. The method of claim 1, wherein the automatically generating, the receiving, the mapping, the selecting, and the applying steps are repeated until

the one or more hardware performance characteristics satisfies a specified performance constraint, or

a termination criterion is met.

10. The method of claim 9, wherein the specified performance constraint is one or more of:

a timing constraint for the synthesized hardware component,

an area constraint for the synthesized hardware component, and

a power constraint for the synthesized hardware component.

11. The method of claim 9, wherein the termination criterion represents an achievement of a best solution for the specified performance constraint.

12. The method of claim 1, further comprising:

generating a revised executable model from the revised intermediate representation; and

presenting the revised executable model to an output device.

13. The method of claim 9, wherein the revised executable model includes a plurality of model elements, the method further comprising:

associating the one or more hardware performance characteristics with one or more of the plurality of model elements of the revised executable model.

14. An apparatus comprising:

a memory storing a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model; and

one or more processors configured to;

automatically generate hardware description language (HDL) code from the first intermediate representation;

receive one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code;

map the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation;

select an optimization technique;

apply the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption;

repeat the automatically generate, the receive, the map, the select, and the apply steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code; and

configure a target programmable hardware element based on the HDL code or the revised HDL code.

15. The apparatus of claim 14, wherein the one or more processors are further configured to:

map the one or more hardware performance characteristics received from the hardware synthesis tool to portions of the HDL code or the revised HDL code; and

trace the one or more hardware performance characteristics, as mapped to the portions of the HDL code or the revised HDL code, back to the first intermediate representation.

16. The apparatus of claim 15, wherein the HDL code or the revised HDL code includes function names and variable names, and the one or more processors are further configured to:

at least one of prepend or append predetermined delimiters to the function names and to the variable names; and

locate occurrences of the predetermined delimiters in the one or more hardware performance characteristics, where

the mapping of the one or more hardware performance characteristics to the portions of the HDL code or the revised HDL code is based on the occurrences of the predetermined delimiters located in the one or more hardware performance characteristics.

17. The apparatus of claim 14, wherein the one or more hardware performance characteristics are included in a hardware synthesis report produced by the hardware synthesis tool, and the one or more processors are further configured to:

utilize a communication interface coupled to the hardware synthesis tool to obtain at least a portion of the hardware synthesis report.

18. One or more non-transitory computer-readable media comprising program instructions, the program instructions when executed by a processor operable to:

store, in a memory accessible by the processor, a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model;

automatically generate hardware description language (HDL) code from the first intermediate representation;

receive one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code;

map the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation;

select an optimization technique;

apply the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption; and

repeat the automatically generate, the receive, the map, the select, and the apply steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code, wherein

a programmable hardware element is configured based on the HDL code or the revised HDL code.

19. The one or more non-transitory computer-readable media of claim 18 further comprising program instructions to:

map the one or more hardware performance characteristics received from the hardware synthesis tool to portions of the HDL code or the revised HDL code; and

trace the one or more hardware performance characteristics, as mapped to the portions of the HDL code or the revised HDL code, back to the first intermediate representation.

20. The one or more non-transitory computer-readable media of claim 18, wherein the automatically generate, the receive, the map, the select, and the apply steps are repeated until

the one or more hardware performance characteristics satisfies a specified performance constraint, or

a termination criterion is met.

21. The one or more non-transitory computer-readable media of claim 18 further comprising program instructions to:

receive timing information from the hardware synthesis tool; and

identify a critical path in the executable model based on the timing information.

22. The one or more non-transitory computer-readable media of claim 18 further comprising program instructions to:

generate a genealogy graph configured to provide a temporal representation of the plurality of nodes included in the first intermediate representation and intermediate representation nodes in the revised intermediate representation.

23. The one or more non-transitory computer-readable media of claim 22, wherein the program instructions to map include program instructions to:

utilize the genealogy graph to back annotate the first intermediate representation or the revised intermediate representations with the one or more hardware performance characteristics.

24. The one or more non-transitory computer-readable media of claim 18, wherein the one or more hardware performance characteristics are included in a hardware synthesis report produced by the hardware synthesis tool, the one or more non-transitory computer-readable media further comprising program instruction to:

utilize an Application Programming Interface (API) of the hardware synthesis tool to obtain at least a portion of the hardware synthesis report.

25. The one or more non-transitory computer-readable media of claim 18, wherein the program instructions to automatically generate, receive, map, select, and apply are repeated until

the one or more hardware performance characteristics satisfies a specified performance constraint, or

a termination criterion is met.

26. The one or more non-transitory computer-readable media of claim 25, wherein the specified performance constraint is one or more of:

a timing constraint for the synthesized hardware component,

an area constraint for the synthesized hardware component, and

a power constraint for the synthesized hardware component.

27. The one or more non-transitory computer-readable media of claim 25, wherein the termination criterion represents an achievement of a best solution for the specified performance constraint.

28. The one or more non-transitory computer-readable media of claim 18 further comprising program instructions to:

generate a revised executable model from the revised intermediate representation; and

present the revised executable model to an output device.

29. The one or more non-transitory computer-readable media of claim 28, wherein the revised executable model includes a plurality of model elements, the one or more non-transitory computer-readable media further comprising program instructions to:

associate the one or more hardware performance characteristics with one or more of the plurality of model elements of the revised executable model.