Systems and methods for generating optimized hardware descriptions for models
First Claim
1. A method comprising:
- storing in a memory a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model;
automatically generating, by a processor configured to access the first intermediate representation from the memory, hardware description language (HDL) code from the first intermediate representation;
receiving one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code;
mapping the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation;
selecting, by the processor, an optimization technique;
applying the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption;
repeating the automatically generating, the receiving, the mapping, the selecting, and the applying steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code; and
configuring a programmable hardware element based on the HDL code or the revised HDL code.
1 Assignment
0 Petitions
Accused Products
Abstract
Systems and methods automatically generate optimized hardware description language (HDL) code for an executable model. An intermediate representation is generated for the executable model, which includes model elements. The intermediate representation includes nodes corresponding to the model elements. The HDL code is generated from the intermediate representation. A synthesis tool chain performs hardware synthesis using the HDL code. The synthesis tool chain generates performance characteristics of hardware components defined by the synthesis tool chain. The performance characteristics are mapped to the nodes of the intermediate representation, and one or more performance bottlenecks are identified. At least one optimization technique is applied to the intermediate representation to produce a revised intermediate representation, which is then used to generate new HDL code. The process may be repeated until the performance bottlenecks are eliminated or a termination criterion is met.
-
Citations
29 Claims
-
1. A method comprising:
-
storing in a memory a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model; automatically generating, by a processor configured to access the first intermediate representation from the memory, hardware description language (HDL) code from the first intermediate representation; receiving one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code; mapping the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation; selecting, by the processor, an optimization technique; applying the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption; repeating the automatically generating, the receiving, the mapping, the selecting, and the applying steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code; and configuring a programmable hardware element based on the HDL code or the revised HDL code. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. An apparatus comprising:
-
a memory storing a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model; and one or more processors configured to; automatically generate hardware description language (HDL) code from the first intermediate representation; receive one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code; map the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation; select an optimization technique; apply the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption; repeat the automatically generate, the receive, the map, the select, and the apply steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code; and configure a target programmable hardware element based on the HDL code or the revised HDL code. - View Dependent Claims (15, 16, 17)
-
-
18. One or more non-transitory computer-readable media comprising program instructions, the program instructions when executed by a processor operable to:
-
store, in a memory accessible by the processor, a first intermediate representation of an executable model having a plurality of model elements, the first intermediate representation including a plurality of nodes corresponding to the plurality of model elements of the executable model; automatically generate hardware description language (HDL) code from the first intermediate representation; receive one or more hardware performance characteristics, generated by a hardware synthesis tool, of a hardware component synthesized from the HDL code; map the one or more hardware performance characteristics generated by the hardware synthesis tool to two or more of the plurality of nodes of the first intermediate representation; select an optimization technique; apply the selected optimization technique to the first intermediate representation to generate a revised intermediate representation improved for one or more of timing, area usage, or power consumption; and repeat the automatically generate, the receive, the map, the select, and the apply steps using the revised intermediate representation in place of the first intermediate representation to produce revised HDL code, wherein a programmable hardware element is configured based on the HDL code or the revised HDL code. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
-
Specification