Multi-FPGA prototyping of an ASIC circuit

• US 9,817,934 B2
• Filed: 07/26/2016
• Issued: 11/14/2017
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Marrakchi, Zied, Alexandre, Christophe
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US15/220,368
• Publication Number:
  US 20170053052A1
• Time in Patent Office: 476 Days
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

The invention concerns a method of designing a prototype comprising a plurality of programmable chips, such as FPGA chips, for modelling an ASIC circuit, said ASIC circuit being intended to implement a logic design comprising a hierarchy of logic modules communicating together. The method according to the invention comprises steps of: —partitioning the hierarchy of logic modules into regions each comprising one or a plurality of programmable chips, while minimising: —inter-region communications in a manner correlated to the physical connections available between each pair of programmable chips; —and the number of crossings of programmable chips of a critical combinatorial path; —establishing a routing of the signals between programmable chips using the physical resources available.

Claims

1. A method of generating configuration data for a prototype, the prototype comprising a plurality of programmable devices interconnected by a plurality of physical tracks, the method comprising:

receiving, using a computer, a logic design for implementation on the prototype, the logic design comprising a hierarchy of interconnected logic modules;

creating, using the computer, a new hierarchy of logic modules comprising a group of logic modules preserved from the received logic design and flattened logic corresponding to logic modules from the received logic design that are flattened;

partitioning, using the computer, the new hierarchy of logic modules into regions, each region comprising one or more programmable chips, while reducing a cost function based on a number of multiplexed signals of a critical combinatorial path and an amount of inter-region communications on the physical tracks connecting the programmable devices; and

generating, using the computer, the configuration data for the prototype, the configuration data comprising routing assignments among the programmable devices using the physical tracks of the prototype.

2. The method of claim 1, wherein generating the routing assignments comprises selecting between board physical tracks and cables between the programmable devices.

3. The method of claim 1, wherein generating the routing assignments comprises multiplexing signals on a board physical track.

4. The method of claim 3, wherein a multiplexing ratio is reduced by routing through other programmable chips to reach a final destination.

5. The method of claim 1, wherein generating the routing assignments comprises representing resources of a board of the prototype by a graph in which nodes of the graph are pins of the programmable devices and edges of the graph are the physical tracks.

6. The method of claim 1, wherein the cost function is further based on one of a user design constraint or a resource constraint of a given programmable device of the plurality of the programmable devices.

7. The method of claim 1, wherein the plurality of programmable devices comprises a field programmable gate array (FPGA).

8. A computer-readable memory storing computer-executable instructions for executing the method of claim 1.

9. A computer configured to execute a method, the method comprising:

receiving, using the computer, a logic design for implementation on a prototype comprising a plurality of programmable devices interconnected by a plurality of physical tracks, the logic design comprising a hierarchy of interconnected logic modules;

flattening, using the computer, logic modules of the logic design that cannot meet a design constraint of the respective programmable devices;

creating, using the computer, a new hierarchy of logic modules comprising the flattened logic modules and preserved logic modules of the logic design;

partitioning, using the computer, the new hierarchy of logic modules into regions, a respective region comprising one or more of the programmable devices, while reducing multiplexed signals and a number of traversals of programmable devices of a critical combinatorial path of the logic design; and

creating, using the computer, a routing of signals between the programmable chips of the prototype by using the physical tracks of the prototype.

10. The computer of claim 9, wherein creating the routing assignments comprises selecting between board physical tracks and cables between the programmable devices.

11. The computer of claim 9, wherein generating the routing assignments comprises multiplexing signals on a board physical track.

12. The computer of claim 9, wherein a multiplexing ratio is reduced by routing through other programmable chips to reach a final destination.

13. The computer of claim 9, wherein generating the routing assignments comprises representing resources of a board of the prototype by a graph in which nodes of the graph are pins of the programmable devices and edges of the graph are the physical tracks.

14. The computer of claim 9, wherein the cost function is further based on one of a user design constraint or a resource constraint of a given programmable device of the plurality of the programmable devices.

15. The computer of claim 9, wherein the plurality of programmable devices comprises a field programmable gate array (FPGA).

16. A prototyping system for implementing a design comprising a hierarchy of design modules, the prototyping system comprising:

a board comprising physical tracks; and

a plurality of programmable devices being interconnected by the physical tracks, respective programmable devices of the plurality of programmable devices being configured by a method comprising;

preserving a first group of the design modules;

flattening a second group of the design modules;

creating a new hierarchy of design modules comprising the first group of the preserved design modules and the second group of the flattened design modules;

partitioning the new hierarchy of design modules into regions while reducing a cost function based on a number of multiplexed signals and a number of traversals of programmable devices of a critical path; and

creating a routing of signals between the programmable devices.

17. The prototyping system of claim 16, wherein a plurality of pins of a respective programmable device is connected to a connector configured to connect to a cable, and the cable connects the respective programmable device to another programmable device.

18. The prototyping system of claim 17, wherein creating the routing of signals comprises selecting between the physical tracks of the board and the cable.

19. The prototyping system of claim 16, wherein creating the routing of signals comprises multiplexing signals on the physical tracks of the board.

20. The prototyping system of claim 19, wherein a multiplexing ratio is reduced by going through other programmable devices to reach a final destination.