Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs
First Claim
1. A computer implemented method for implementing additional connectivity for an electronic design, comprising:
- using at least one processor or at least one processor core to perform a process the process comprising;
identifying one or more regions for a route in normal connectivity that is accessible by a connectivity iterator module that iterates over a first plurality of geometric entities for an electronic design;
identifying a plurality of seeding segments from the route based at least in part upon the one or more regions;
generating, at a different connectivity iterator module, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and
implementing a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator module from the physical design based at least in part upon the plurality of additional nodes.
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Accused Products
Abstract
Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.
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Citations
20 Claims
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1. A computer implemented method for implementing additional connectivity for an electronic design, comprising:
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using at least one processor or at least one processor core to perform a process the process comprising; identifying one or more regions for a route in normal connectivity that is accessible by a connectivity iterator module that iterates over a first plurality of geometric entities for an electronic design; identifying a plurality of seeding segments from the route based at least in part upon the one or more regions; generating, at a different connectivity iterator module, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and implementing a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator module from the physical design based at least in part upon the plurality of additional nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system for implementing additional connectivity for an electronic design, comprising:
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at least one processor or at least one processor core that is at least to; identify one or more regions for a route in normal connectivity that is accessible by a connectivity iterator that iterates over a first plurality of geometric entities for an electronic design; identify a plurality of seeding segments from the route based at least in part upon the one or more regions; generate, at a different connectivity iterator, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and implement a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator from the physical design based at least in part upon the plurality of additional nodes. - View Dependent Claims (17, 18)
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19. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a process for implementing additional connectivity for an electronic design, the process comprising:
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identifying one or more regions for a route in normal connectivity that is accessible by a connectivity iterator module that iterates over a first plurality of geometric entities for an electronic design; identifying a plurality of seeding segments from the route based at least in part upon the one or more regions; generating, at a different connectivity iterator module, one or more additional routes in different connectivity that is different from the normal connectivity and is accessible by the different connectivity iterator module for the electronic design; and implementing a physical design of the electronic design at least by removing one or more redundancies or one or more loops with the different connectivity iterator module from the physical design based at least in part upon the plurality of additional nodes. - View Dependent Claims (20)
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Specification