Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation
First Claim
1. A method, comprising:
- maintaining neuron information for multiple neurons of a neural network;
maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and
based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network;
wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed.
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Abstract
Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation. One embodiment comprises a neurosynaptic device including a memory device that maintains neuron attributes for multiple neurons. The module further includes multiple bit maps that maintain incoming firing events for different periods of delay and a multi-way processor. The processor includes a memory array that maintains a plurality of synaptic weights. The processor integrates incoming firing events in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes and the synaptic weights maintained.
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Citations
15 Claims
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1. A method, comprising:
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maintaining neuron information for multiple neurons of a neural network; maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network; wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed. - View Dependent Claims (2, 3, 4, 5)
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6. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising:
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maintaining neuron information for multiple neurons of a neural network; maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network; wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed. - View Dependent Claims (7, 8, 9, 10)
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11. A non-transitory computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising:
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maintaining neuron information for multiple neurons of a neural network; maintaining incoming firing events for different periods of delay in a set of bit maps, wherein each bit map of the set of bit maps corresponds to a period of delay of the different periods of delay, and the bit map indicates which incoming axon of multiple incoming axons of the neural network receives an incoming firing event in a future time step that occurs after the corresponding period of delay has elapsed; and based on the neuron information and the set of bit maps, integrating incoming firing events in a time-division multiplexing manner using multiple processors of the neural network; wherein the total number of neurons in the neural network is based on the number of processors in the neural network and the number of times each processor is time-multiplexed. - View Dependent Claims (12, 13, 14, 15)
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Specification